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BusWrapper API Update #1190

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merged 17 commits into from
Mar 1, 2018
Merged

BusWrapper API Update #1190

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8462ea3
coreplex => subsystem
hcook Jan 12, 2018
3f436a7
subsystem: new bus attachment api
hcook Feb 15, 2018
62aee56
diplomacy: base instance names on ValName and module names on className
hcook Feb 16, 2018
ef3adde
diplomacy: put full module + instance path into graphml Description
terpstra Dec 1, 2017
57edd7f
subsystem: streamline toTile and fromTile attachment
hcook Feb 16, 2018
a6d3965
tilelink: bus wrapper scopes called 'couplers'
hcook Feb 17, 2018
b617e26
util: augment String and use to name couplers
hcook Feb 21, 2018
030c6f0
subsystem: bus wrappers now in BaseSubsystem
hcook Feb 21, 2018
1af02f7
groundtest: fix filename
hcook Feb 21, 2018
e237f72
subsystem: XSubsystemModule => XSubsystemModuleImp
hcook Feb 21, 2018
eaa908d
subsystem: more buswrapper methods
hcook Feb 21, 2018
78883d1
subsystem: add TLIdentity.gen and make wrappers more flexible
hcook Feb 22, 2018
099bbec
subsystem: more buswrapper coupling methods
hcook Feb 23, 2018
5b1d72c
subsystem: expose HasTiles Parameters
hcook Feb 23, 2018
5725e17
subsystem: even more general coupler methods
hcook Feb 23, 2018
ad823ef
subsystem: pbus crossing type
hcook Feb 23, 2018
30c0635
subsystem: add some inter-wrapper buffer params
hcook Feb 23, 2018
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2 changes: 1 addition & 1 deletion src/main/scala/amba/axi4/AsyncCrossing.scala
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Expand Up @@ -7,7 +7,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.coreplex.{CrossingWrapper, AsynchronousCrossing}
import freechips.rocketchip.subsystem.{CrossingWrapper, AsynchronousCrossing}

class AXI4AsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
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55 changes: 0 additions & 55 deletions src/main/scala/coreplex/FrontBus.scala
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79 changes: 0 additions & 79 deletions src/main/scala/coreplex/MemoryBus.scala
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61 changes: 0 additions & 61 deletions src/main/scala/coreplex/PeripheryBus.scala
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83 changes: 0 additions & 83 deletions src/main/scala/coreplex/SystemBus.scala
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9 changes: 3 additions & 6 deletions src/main/scala/devices/debug/Periphery.scala
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Expand Up @@ -5,7 +5,7 @@ package freechips.rocketchip.devices.debug
import Chisel._
import chisel3.core.{IntParam, Input, Output}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.jtag._
Expand All @@ -26,12 +26,9 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), based on a global parameter.
*/
trait HasPeripheryDebug extends HasPeripheryBus {
val module: HasPeripheryDebugModuleImp

trait HasPeripheryDebug { this: BaseSubsystem =>
val debug = LazyModule(new TLDebugModule(pbus.beatBytes))

debug.node := pbus.toVariableWidthSlaves
pbus.toVariableWidthSlave(Some("debug")){ debug.node }
}

trait HasPeripheryDebugBundle {
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10 changes: 5 additions & 5 deletions src/main/scala/devices/tilelink/BootROM.scala
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Expand Up @@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink

import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem.{BaseSubsystem, HasResetVectorWire}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
Expand Down Expand Up @@ -58,8 +58,8 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
}
}

/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
trait HasPeripheryBootROM extends HasPeripheryBus {
/** Adds a boot ROM that contains the DTB describing the system's subsystem. */
trait HasPeripheryBootROM { this: BaseSubsystem =>
val dtb: DTB
private val params = p(BootROMParams)
private lazy val contents = {
Expand All @@ -71,10 +71,10 @@ trait HasPeripheryBootROM extends HasPeripheryBus {

val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))

bootrom.node := pbus.toVariableWidthSlaves
pbus.toVariableWidthSlave(Some("bootrom")){ bootrom.node }
}

/** Coreplex will power-on running at 0x10040 (BootROM) */
/** Subsystem will power-on running at 0x10040 (BootROM) */
trait HasPeripheryBootROMModuleImp extends LazyModuleImp
with HasResetVectorWire {
val outer: HasPeripheryBootROM
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1 change: 0 additions & 1 deletion src/main/scala/devices/tilelink/BusBypass.scala
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Expand Up @@ -4,7 +4,6 @@ package freechips.rocketchip.devices.tilelink

import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
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