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Convert Debug Module to abstract reset #2237
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Reduce size of Bypass logic in debug modoule Parameterize atomics and transferSize in TLBusBypassBase, set in dmOuterAsync Bus Blocker: BriskBusBlocker is very similar to TLBusBlocker
…t that async crossings are truly async and marked with SynchronizerPrimitiveShiftReg
…gSink API for asynchronous interrupt crossings
Correct the minLatency for TLZero back to 1
…ebug-abstract-reset
Adds LazyModule.withClock, LazyModule.withReset, and LazyModule.withClockAndReset to support setting custom clocks and resets for LazyModuleImps
Included in #2375 |
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Type of change: feature request
Impact: API modification
Development Phase: implementation
Release Notes
This PR converts the debug module to the new Configurable Reset Scheme using chisel3 abstract reset.
dmi_clock
anddmi_reset
and dmInner uses new inputsdebug_clock
anddebug_reset
. A portion of SBA is in the TileLinkclock
/reset
domain.debug_clock
must be synchronous toclock
. The clock gate formerly in dmInnerAsync now resides outside the debug module in customer logic. Customer logic can callconnectDebugClockAndReset
to achieve the same functionality as before.dmactiveAck
is returned from customer logic and is used to indicate when dmInner is able to accept DMI transactions (i.e.debug_clock
is running anddebug_reset
is negated). WhendmactiveAck
is negated, a bus blocker returnsdenied
for transactions to dmInner. The current version of OpenOCD is tolerant of this blocker, but other software may need to be updated.dmi_reset
must be asynchronous.debug_reset
may be either synchronous or asynchronous but its deassertion must always occur either whendebug_clock
is stopped or synchronously todebug_clock
.ResetCtrlIO
bundle.hartIsInReset
is a logical equivalent ofcore_reset
and is synchronous tocore_clock
. For debug module halt-on-reset function, this signal must remain asserted for at least 4debug_clock
cycles for the DM to assert debug interrupt plus 3core_clock
cycles for the debug interrupt to reach the core prior to thecore_reset
signal being deasserted. Halt-on-reset will not work if eitherclock
orcore_clock
is not running.clock
andreset
signals formerly inTracedInstruction
have been removed since a trace module attached would not be allowed to use them because of the 1:1 rule.AsyncResetReg
instantiations have been changed to abstract reset.This PR includes cherry-picks from these other branches:
SynchronizerShiftReg
replaced by versions which specify the type of reset to be applied to the internal registers.dmactive
. This PR modifies the control to include bothdmactive
and a synchronized version ofdmactiveAck
.reset
aReset()
rather than aBool()
.AsyncReset
registers when the initializer is a literal cast to a Bundle.There are still a few issues to resolve:
AsyncReset
andBool
). We need this function to properly use reset type inference in the debug module hierarchy. --> Edit: this has been done in the bump-firrtl branch.require()
statement).core_clock
to be running prior to deassertingcore_reset
. Without this, the core will not halt prior to executing the first instruction.