Remove redundant TLBExceptions V bit #3246
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
Do not merge yet, blocked by #3243 |
ZenithalHourlyRate
force-pushed
the
fix-tlbresp-v-bit
branch
from
d08ed4a
to
8611f0c
Compare
sequencer
force-pushed
the
fix-tlbresp-v-bit
branch
from
8611f0c
to
5261102
Compare
This was introduced by "(185cac8) Add hypervisor extension (#2841)" This is a dead code, as no circuit is producing and consuming this bit. This was discovered when migrating Core.scala to chisel3, where strict checking was applied for IO and firrtl found this is not connected. In the context of hypervisor extension, V bit, or _virtualization mode_, indicates whether the hart is currently executing in a guest. For TLBReq, the V bit is needed as it affects the PTW thus TLB behavior on whether to do _Two-Stage Address Translation_. However, the bit is not needed for TLBException. The exceptions (pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point to add V bit for gf (guest page fault). The io.resp.gf added below in the original patch also does not connect io.resp.gf.v. If this V bit should be added for this specific exception, it should be connected. I assume this was added accidentally, as the original "extends CoreBundle()(p)" modification seems irrelevant.
sequencer
force-pushed
the
fix-tlbresp-v-bit
branch
from
5261102
to
666c32d
Compare
sequencer
approved these changes
Feb 22, 2023
Merged
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This was introduced by "(185cac8) Add hypervisor extension (#2841)"
This is a dead code, as no circuit is producing and consuming this bit.
This was discovered when migrating Core.scala to chisel3, where strict checking was applied for IO and firrtl found this is not connected.
In the context of hypervisor extension, V bit, or virtualization mode, indicates whether the hart is currently executing in a guest.
For TLBReq, the V bit is needed as it affects the PTW thus TLB behavior on whether to do Two-Stage Address Translation.
However, the bit is not needed for TLBException. The exceptions (pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point to add V bit for gf (guest page fault).
The io.resp.gf added below in the original patch also does not connect io.resp.gf.v. If this V bit should be added for this specific exception, it should be connected.
I assume this was added accidentally, as the original "extends CoreBundle()(p)" modification seems irrelevant.
Related issue:
Type of change: bug report
Impact: no functional change
Development Phase: implementation
Release Notes