Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add customDecoder interface to rocket #3564

Open
wants to merge 1 commit into
base: dev
Choose a base branch
from
Open

Add customDecoder interface to rocket #3564

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 7 additions & 1 deletion src/main/scala/rocket/RocketCore.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,8 @@ case class RocketCoreParams(
fpu: Option[FPUParams] = Some(FPUParams()),
debugROB: Boolean = false, // if enabled, uses a C++ debug ROB to generate trace-with-wdata
haveCease: Boolean = true, // non-standard CEASE instruction
haveSimTimeout: Boolean = true // add plusarg for simulation timeout
haveSimTimeout: Boolean = true, // add plusarg for simulation timeout
customDecoder: Option[UInt => IntCtrlSigs] = None // custom decoder implementation
) extends CoreParams {
val lgPauseCycles = 5
val haveFSDirty = false
Expand Down Expand Up @@ -298,6 +299,11 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point")
require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor")
val id_ctrl = Wire(new IntCtrlSigs(aluFn)).decode(id_inst(0), decode_table)
if (rocketParams.customDecoder.isDefined) {
id_ctrl := rocketParams.customDecoder.get(id_inst(0))
} else {
id_ctrl.decode(id_inst(0), decode_table)
}
val lgNXRegs = if (coreParams.useRVE) 4 else 5
val regAddrMask = (1 << lgNXRegs) - 1

Expand Down
Loading