Compile error with Yosys 0.37

[hzeller]

Compiling with yosys 0.37, current synlig has a compile issue:

/build/source/frontends/systemverilog/uhdm_common_frontend.cc: In member function 'virtual void systemverilog_plugin::UhdmCommonFrontend::execute(std::istream*&, std::string, std::vector<std::__cxx11::basic_string<char> >, Yosys::RTLIL::Design*)':
/build/source/frontends/systemverilog/uhdm_common_frontend.cc:154:21: error: too few arguments to function 'void Yosys::AST::process(Yosys::RTLIL::Design*, AstNode*, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool)'
  154 |         AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, false, false, false, false, false,
      |         ~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  155 |                      false, false, false, false, false, dont_redefine, false, defer, default_nettype_wire);
      |                      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

After fixing here, we should consider sending an upstream patch to yosys: passing a myriad of boolean parameters to process() is somewhat fragile. Instead, passing a struct with values that already have a good default is probably much better.