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[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class. #1376
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Commits on Jul 21, 2022
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constructing the control flow tree, to enable the preprocessor tool t…
…o generate all variants with the new mode generate-variants
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Commits on Jul 22, 2022
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using ABSL flags in preprocessor tool, edited the tool test just to p…
…ass for the moment.
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Commits on Jul 25, 2022
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Adding a new common util class.
"verible::CmdPositionalArguments" class only supports these types so far: SV files, +define+<name>[=<value>], and +incdir+<dir>.
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- Adding an interface function "AddDefineFromCmdLine" to use the macro added by +define+<foo> argument to "VerilogPreprocess".
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Commits on Jul 27, 2022
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- Added a feature to VerilogPreprocess which allows to store paths, That can be used later to find the SV file to include. - The preprocessor tool takes these paths from the user, as a +incdir+<path>[+<another_path>] and set then in VerilogPreprocess. - The included files macros and conditionals can be expanded and evaluated. - Some limitations exists and were written as TODOs in place, need to open issues for these.
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Commits on Jul 29, 2022
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- The preprocessor tool preserves the white-spaces in the SV files. - Changed the output of the -generate_variants and -multipecu from tokens (enum,text) into normal text.
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