RISC-V Architecture Implementation

Objective

The goal of this project is to explore a non-traditional computer architecture and implement a program or benchmark on an FPGA.

Project Deliverables

• A processor on an FPGA that executes a simple instruction set that, in theory, can execute each of the C benchmarks
• A benchmark that executes on the architecture
• A series of micro-benchmarks that executes on the architecture to show that the processor works for all instructions and all paths are exercised on the processor

Approach to Creating My Computer Architecture

My plan:

• Read through and understand Tiny RISC-V ISA
• Practice creating programs with RISC-V on RARS
• Make RISC-V benchmark(s) that cover all of the Tiny RISC-V ISA
• (Very very simply put) Create processor on an FPGA using Quartus and Verilog that will execute the Tiny RISC-V ISA and C benchmarks

Regarding last step:

• Decide on encoding rules to use (I decided on using the Tiny RISC-V ISA encoding)
• Create ALU that executes different instructions
• Create register file that covers all registers
• Create control that connects everything

Steps I took to develop my architecture:

1. Read through the Tiny RISC-V ISA and worked to understand it
2. Created assembly benchmarks to test all the Tiny RISC-V instructions
3. Created spreadsheet to keep track of instructions I need to implement
4. Created ALU module in verilog
5. Created Register module in verilog
6. Created Control module in verilog
7. Edited Control and ALU modules as I debugged
8. Updated my master project spreadsheet as I implement more instructions
9. Made test cases (documented on this google spreadsheet) and fixed verilog program as needed
10. Demoed my architecture to my professor

Project Overview

Modules:

Control.v

• Top module
• Holds FSM that controls entire program
• Reads in 32 bit instruction and executes whatever the instruction intends for

ALU.v

• Arithmetic logic unit
• Completes different arithmetic functions based on input encodings

Register.v

• Simple register module

tb_control.v

• Testbench for project

instructions_mem.v

• On-chip 1 port RAM memory used to hold the input instructions for the program

main_mem.v

• On-chip 1 port RAM memory used as main memory that can be written to and read from

How I Tested My Architecture

Process:

1. Created RISC-V assembly benchmark on RARS
2. Put the instructions in a google spreadsheet and coverted the encoding hex numbers to decimal
3. Put the decimal instructions into a .mif file
4. Ran ModelSim using the testbench tb_control.v
5. Verified the ModelSim results match the RARS results

Test 1: Pop Count

• Assembly program: pop_count.asm
• Spreadsheet:

  

• Mif file: pop_count.mif

  

• ModelSim:

  

  - result_t0: holds the number being "pop counted" and the shifted values from each iteration
  - result_t1: holds the count of 1s after each iteration
  - result_t2: holds the iterating value for the for loop
  - result_t3: holds the total value to iterate to in the for loop
  - result_t4: holds the current least significant bit value from each iteration
  - result_t5: holds the total count of 1s at the end of the program
  

Test 2: Five Factorial

• Assembly program: factorial.asm
• Spreadsheet:

  

• Mif file: factorial.mif

  

• ModelSim:

  

  - result_t0: holds the factorial number being multiplied from each iteration
  - result_t1: holds the number multiplying into the factorial number
  - result_t2: holds the final factorial at the end of the program
  

Test 3: Store Word/Load Word

• Assembly program: sw_lw.asm
• Spreadsheet:

  

• Mif file: sw_lw.mif

  

• ModelSim:

  

  - result_t0: holds the number (3) being used as a condition in the while loops
  - result_t1: holds the number (1) being used in sub because there was no subi (subtract immediate) in the Tiny RISC-V ISA
  - result_t2: holds the changing number that is to be stored into and loaded from main memory
  - result_t3: holds holds the numbers being loaded from main memory
  - result_t4: holds the number which has the loaded numbers subtracted from it
  - result_t5: holds the resulting number from result_t4 at the end of the program
  

Test 4: Big Test

This test covered the rest of the instructions not already covered in the previous 3 tests.

• Assembly program: big_test.asm
• Spreadsheet:

  
  

• Mif file: big_test.mif

  

• ModelSim:

  

  - result_t0: holds the iterating number used in the for loop and inside if statements to determine which option to execute
  - result_t1 - result_t6: hold values for all of the different operations executed throughout the program
  

Resources:

• RARS
• Tiny RISC-V ISA