Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix and document Altera PLL's #2136

Merged
merged 1 commit into from
Mar 24, 2022
Merged

Fix and document Altera PLL's #2136

merged 1 commit into from
Mar 24, 2022

Conversation

DigitalBrains1
Copy link
Member

@DigitalBrains1 DigitalBrains1 commented Mar 23, 2022

Commit d325557 introduced an off-by-one error in the number of clocks
to generate for alteraPll.

Additionally, the internal locked signal for alteraPll is changed to
be of type Bit like in altpll. The borrowing of the type of the
Reset input probably came about out of convenience back when resets
were still a simple type so it did not matter. Now it looked odd but
worked fine nonetheless.

Also adjusted the type in CondAssignment in altpll, which showed the
same pattern.

Still TODO:

  • Write a changelog entry (see changelog/README.md)
  • Check copyright notices are up to date in edited files

Copy link
Contributor

@alex-mckenna alex-mckenna left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM. While we're editing around here though: is it worth referring users to look at the data sheet to see what clocks they can ask for. I assume the speed of clocks you can generate is determined by the board you're using or something? Even if it's obvious to hardware engineers, it feels like something that makes it friendlier to hobbyists etc.

@alex-mckenna
Copy link
Contributor

This is what you get for recently doing a documentation PR, I actually thought about the documentation while reviewing 😉

@DigitalBrains1
Copy link
Member Author

Okay, you motivated me to write more documentation for this module. How's this? (note: build artifact of CI, will disappear next time CI runs for this PR)

@alex-mckenna
Copy link
Contributor

This looks much better to me, but I think @leonschoorl or @christiaanb should give it a quick skim too in case I've missed something obvious (or worse, something subtle)

@DigitalBrains1 DigitalBrains1 changed the title Fix and document alteraPll primitive Fix and document Altera PLL's Mar 24, 2022
Commit d325557 introduced an off-by-one error in the number of clocks
to generate for 'alteraPll'.

Additionally, the internal `locked` signal for `alteraPll` is changed to
be of type `Bit` like in `altpll`. The borrowing of the type of the
`Reset` input probably came about out of convenience back when resets
were still a simple type so it did not matter. Now it looked odd but
worked fine nonetheless.

Also adjusted the type in `CondAssignment` in `altpll`, which showed the
same pattern.
@DigitalBrains1 DigitalBrains1 merged commit 9417cb6 into master Mar 24, 2022
@DigitalBrains1 DigitalBrains1 deleted the alterapll branch March 24, 2022 14:53
mergify bot pushed a commit that referenced this pull request Mar 24, 2022
Commit d325557 introduced an off-by-one error in the number of clocks
to generate for `alteraPll`.

Additionally, the internal `locked` signal for `alteraPll` is changed to
be of type `Bit` like in `altpll`. The borrowing of the type of the
`Reset` input probably came about out of convenience back when resets
were still a simple type so it did not matter. Now it looked odd but
worked fine nonetheless.

Also adjusted the type in `CondAssignment` in `altpll`, which showed the
same pattern.

(cherry picked from commit 9417cb6)
DigitalBrains1 added a commit that referenced this pull request Mar 24, 2022
Commit d325557 introduced an off-by-one error in the number of clocks
to generate for `alteraPll`.

Additionally, the internal `locked` signal for `alteraPll` is changed to
be of type `Bit` like in `altpll`. The borrowing of the type of the
`Reset` input probably came about out of convenience back when resets
were still a simple type so it did not matter. Now it looked odd but
worked fine nonetheless.

Also adjusted the type in `CondAssignment` in `altpll`, which showed the
same pattern.

(cherry picked from commit 9417cb6)

Co-authored-by: Peter Lebbing <peter@digitalbrains.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

3 participants