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Cocotb is tool that allows users to write test benches for HDL in Python. It is much easier to write extensive tests with Python than with verilog.
The following tests should be written an exercise before the sata core is verified:
Bootup: The system starts in a default state How is this defined?
Single Word Write: Write a single piece of data to the SATA stack side: Expected Results: observe the correct address and data on the simulated hard drive
Single Word Read: Read a single piece of data from the SATA stack: Expected Results: observe the correct address on the hard drive side and pass a piece of data through the simulated hard drive and read it from the SATA stack
Large Write: how big? Send a stream of data from the SATA stack side to the simulated hard drive side: Expected Results: observe the correct address behavior (starting at every sector) and the correct data flowing through.
Large Read: how big? Read a stream of data from the SATA stack side: Expected Results: observe the correct address behavior (starting at every sector) and the correct data flowing through.
Large Write With Easy Back Pressure: how big? Send a stream of data from the SATA stack side to the simulated hard drive side with simulated stall commands to slow the transfer of data: Expected Results: observe the correct address behavior (starting at every sector) and the correct data flowing through.
Large Read With Easy Back Pressure: how big? Read a stream of data from the SATA stack side with simulated stall commands to emulate back preassure: Expected Results: observe the correct address behavior (starting at every sector) and the correct data flowing through.
Large Write With Hard Back Pressure: how big? Send a stream of data from the SATA stack side to the simulated hard drive side emulate the challenging back pressure (every other clock, ever two clock, etc..): Expected Results: observe the correct address behavior (starting at every sector) and the correct data flowing through.
Large Read With Hard Back Breassure: how big? Read a stream of data from the SATA stack side emulate the challenging back pressure (every other clock, ever two clock, etc..): Expected Results: observe the correct address behavior (starting at every sector) and the correct data flowing through.
The text was updated successfully, but these errors were encountered:
Cocotb is tool that allows users to write test benches for HDL in Python. It is much easier to write extensive tests with Python than with verilog.
The following tests should be written an exercise before the sata core is verified:
The text was updated successfully, but these errors were encountered: