Vector Technology as Implemented for Use with a RISC and SIMD Technology Signal Processor
A vector processor uses long registers addressable by segment-precision, where each segment is n bits wide. The power of a vector processor is that many complex matrix operations, whose algorithms take many scalar CPU instructions and clock cycles to emulate on a regular, personal computer processor, can often times formulate and transfer the correct result in less than a single clock cycle. The impossibility to replicate this precise behavior has paved the way for vendor businesses to protect their systems against hardware emulation since the introduction of display devices rendering three-dimensional graphics. The Nintendo 64 was the first video game system to employ this convenience to their advantage.
Project Reality's Signal Processor
In the engineering make-up of the Nintendo 64 (original codename: Project Reality) is a modified MIPS family revision 4000 co-processor called the "Reality Coprocessor" (RCP). More importantly, the signal processor in this component is responsible for all vector memory operations and transactions, which are almost all impossible to emulate with full accuracy on a scalar, personal computer processor. The vector technology implemented into this design is that accepted from Silicon Graphics, Inc.
RSP Vector Operation Matrices
Here, the entire MIPS R4000 instruction set was modified for very fast, exception-free processing flow, and operation definitions for each instruction do not fall within the scope of this section. Presented instead are layouts of the new instructions added to the scalar unit (those under
SWC2, even though they do interface with the vector unit) and the vector unit (essentially, any instruction under
COP2 whose mnemonic starts with a 'V'). Information of how pre-existing MIPS R4000 instructions were modified or which ones were removed is the adventure of the MIPS programmer to research.
C2 vd, vs, vt[element]
/* exceptions: scalar divide reads */
The major types of VU computational instructions are multiply, add, select, logical, and divide.
Multiply instructions are the most frequent and classifiable as follows:
a == 0, then round the product loaded to the accumulator (
a == 1, then the product is added to an accumulator element (
(format & 0b100) == 0, then the operation is single-precision (
(format & 0b100) != 0, then the operation is double-precision (
00 (VMULF)Vector Multiply Signed Fractions
01 (VMULU)Vector Multiply Unsigned Fractions
VRNDPwas intended for MPEG DCT rounding but omitted.
VMULQwas intended for MPEG inverse quantization but omitted.
04 (VMUDL)Vector Multiply Low Partial Products
05 (VMUDM)Vector Multiply Mid Partial Products
06 (VMUDN)Vector Multiply Mid Partial Products
07 (VMUDH)Vector Multiply High Partial Products
10 (VMACF)Vector Multiply-Accumulate Signed Fractions
11 (VMACU)Vector Multiply-Accumulate Unsigned Fractions
VRNDNwas intended for MPEG DCT rounding but omitted.
13 (VMACQ)Vector Accumulator Oddification
14 (VMADL)Vector Multiply-Accumulate Low Partial Products
15 (VMADM)Vector Multiply-Accumulate Mid Partial Products
16 (VMADN)Vector Multiply-Accumulate Mid Partial Products
17 (VMADH)Vector Multiply-Accumulate High Partial Products
20 (VADD)Vector Add Short Elements
21 (VSUB)Vector Subtract Short Elements
23 (VABS)Vector Absolute Value of Short Elements
24 (VADDC)Vector Add Short Elements with Carry
25 (VSUBC)Vector Subtract Short Elements with Carry
35 (VSAR)Vector Accumulator Read
40 (VLT)Vector Select Less Than
41 (VEQ)Vector Select Equal
42 (VNE)Vector Select Not Equal
43 (VGE)Vector Select Greater Than or Equal
44 (VCL)Vector Select Clip Test Low
45 (VCH)Vector Select Clip Test High
46 (VCR)Vector Select Clip Test Low (single-precision)
47 (VMRG)Vector Select Merge
50 (VAND)Vector AND Short Elements
51 (VNAND)Vector NAND Short Elements
52 (VOR)Vector OR Short Elements
53 (VNOR)Vector NOR Short Elements
54 (VXOR)Vector XOR Short Elements
55 (VNXOR)Vector NXOR Short Elements
60 (VRCP)Vector Element Scalar Reciprocal (single-precision)
61 (VRCPL)Vector Element Scalar Reciprocal Low
62 (VRCPH)Vector Element Scalar Reciprocal High
63 (VMOV)Vector Element Scalar Move
64 (VRSQ)Vector Element Scalar SQRT Reciprocal (single-precision)
65 (VRSQL)Vector Element Scalar SQRT Reciprocal Low
66 (VRSQH)Vector Element Scalar SQRT Reciprocal High
67 (VNOP)Vector Null Instruction
RSP Vector Load Transfers
The VR-DMEM transaction instruction cycles are still processed by the scalar unit, not the vector unit. In the modern implementations accepted by most vector unit communications systems today, the transfer instructions are classifiable under five groups:
- BV, SV, LV, DV
- PV, UV, XV, ZV
- HV, FV, AV
- QV, RV
- TV, WV
Not all of those instructions were implemented as of the time of the Nintendo 64's RCP, however. Additionally, their ordering in the opcode matrix was a little skewed to what is seen below. At this time, it is better to use only three categories of instructions:
- normal: Anything under Group I or Group IV is normal type. Only the element must be aligned;
addr & 1may resolve true.
- packed: Anything under Group II or Group III. Useful for working with specially mapped data, such as pixels.
SWVcan be found in heaps of 16 instructions, all dedicated to matrix transposition through eight diagonals of halfword elements.
LWC2 vt[element], offset(base)
00 (LBV)Load Byte to Vector Unit
01 (LSV)Load Shortword to Vector Unit
02 (LLV)Load Longword to Vector Unit
03 (LDV)Load Doubleword to Vector Unit
04 (LQV)Load Quadword to Vector Unit
05 (LRV)Load Rest to Vector Unit
06 (LPV)Load Packed Signed to Vector Unit
07 (LUV)Load Packed Unsigned to Vector Unit
10 (LHV)Load Alternate Bytes to Vector Unit
11 (LFV)Load Alternate Fourths to Vector Unit
13 (LTV)Load Transposed to Vector Unit
SWC2 vt[element], offset(base)
00 (SBV)Store Byte from Vector Unit
01 (SSV)Store Shortword from Vector Unit
02 (SLV)Store Longword from Vector Unit
03 (SDV)Store Doubleword from Vector Unit
04 (SQV)Store Quadword from Vector Unit
05 (SRV)Store Rest from Vector Unit
06 (SPV)Store Packed Signed from Vector Unit
07 (SUV)Store Packed Unsigned from Vector Unit
10 (SHV)Store Alternate Bytes from Vector Unit
11 (SFV)Store Alternate Fourths from Vector Unit
12 (SWV)Store Transposed Wrapped from Vector Unit
13 (STV)Store Transposed from Vector Unit
If, by any chance, the opcode specifier is greater than 17 [oct], it was probably meant to execute the extended counterparts to the above loads and stores, which were questionably obsolete and remain reserved.
Informational References for Vector Processor Architecture
Instruction Methods for Performing Data Formatting While Moving Data Between Memory and a Vector Register File United States patent no. 5,812,147 Timothy J. Van Hook Silicon Graphics, Inc.
Method and System for Efficient Matrix Multiplication in a SIMD Processor Architecture United States patent no. 7,873,812 Tibet Mimar
Efficient Handling of Vector High-Level Language Constructs in a SIMD Processor United States patent no. 7,793,084 Tibet Mimar
Flexible Vector Modes of Operation for SIMD Processor patent pending? Tibet Mimar
Programming a Vector Processor and Parallel Programming of an Asymmetric Dual Multiprocessor Comprised of a Vector Processor and a RISC Processor United States patent no. 6,016,395 Moataz Ali Mohamed Samsung Electronics Co., Ltd.
Execution Unit for Processing a Data Stream Independently and in Parallel United States patent no. 6,401,194 Le Trong Nguyen Samsung Electronics Co., Ltd.