Clearing Thermal Events may freeze Intel processor families

[cyring]

A list of Intel processors is required to safely allow writing the PROCHOT bit in the following MSR registers:

For both or per Core and per Package.

CoreFreq/corefreqk.c

Line 6652 in 39953f7

WRMSR(ThermStatus, MSR_IA32_THERM_STATUS);

CoreFreq/corefreqk.c

Line 6694 in 39953f7

WRMSR(ThermStatus, MSR_IA32_PACKAGE_THERM_STATUS);

[cyring]

IA32_THERM_INTERRUPT

rdmsr -ax 0x19b
13
13
13
13
13
13
13
13
13
13
13
13

High-Temperature Interrupt Enable = 1
Low-Temperature Interrupt Enable = 1
Critical Temperature Interrupt Enable = 1

• Kernel

mce: CPU0: Thermal monitoring enabled (TM1)

• Interrupt at sysvec_thermal

            CPU0       CPU1       CPU2       CPU3       CPU4       CPU5       CPU6       CPU7       CPU8       CPU9       CPU10      CPU11
 TRM:         50         50         50         50         50         50         50         50         50         50         50         50   Thermal event interrupt

            CPU0       CPU1       CPU2       CPU3       CPU4       CPU5       CPU6       CPU7       CPU8       CPU9       CPU10      CPU11
 TRM:       1690       1690       1690       1690       1690       1690       1690       1690       1690       1690       1690       1690   Thermal event interrupts

• Now attempting to boot with "nomce" > mcheck_cpu_init() to abort __mcheck_cpu_init_vendor() > mce_intel_feature_init(() > intel_init_thermal() > smp_thermal_vector = intel_thermal_interrupt;
• Booting no mce

mce: Unable to init MCE device (rc: -5)

rdmsr -ax 0x19b
10
10
10
10
10
10
10
10
10
10
10
10

High-Temperature Interrupt Enable = 0
Low-Temperature Interrupt Enable = 0
Critical Temperature Interrupt Enable = 1

            CPU0       CPU1       CPU2       CPU3       CPU4       CPU5       CPU6       CPU7       CPU8       CPU9       CPU10      CPU11      
 TRM:          0          0          0          0          0          0          0          0          0          0          0          0   Thermal event interrupts

Clearing log bits

Power Limitation

Thermal Threshold

Thermal Sensor

Conclusions

• Don't clear log bits if Kernel or SMI has set IA32_THERM_INTERRUPT[1-0] for an interrupt handler.

Verifying

1. Stress Processor with Conic Compute > Hyperboloid of two sheets
   
   observe throttling
2. Clear all log bits
   
3. No CPU freeze

[cyring]

• Fix is available for testing since CoreFreq version 1.84.5

• Booting the Kernel with parameter nomce will disable the Interrupt handler installation, and so, thermal log bits can be cleared.

• Thank you for your test reports.