write-barrier slow path sharing CLs did not block LR in all necessary places on ARM

[mraleph]

On ARM we

I see that StoreInstanceFieldInstr takes care to reserve it, but StoreStaticFieldInstr and StoreIndexedInstr does not seem to do the same.

Also I noticed that StoreInstanceFieldInstr has the following problem: even if ShouldEmitStoreBarrier() is false we might still emit a store barrier - because this might be an unboxed store (e.g. obj.field = 2.0) in which case we don't need a store barrier for the value, but we need a store barrier for the temporary box - this means that LR needs to be blocked for these cases as well.

I think StoreIntoObject on ARM needs to assert that object != LR - to make sure that we catch any remaining cases where this does not hold.

[I am marking this as a P0 because this might lead to hard to debug issues where LR is overwritten with strange values]

[rmacnak-google]

Maybe we should we just make LR unavailable to register allocation on ARM like we do on ARM64. It seems easy for all sorts of slow path code to incorrectly assume it's available for making calls.

[mraleph]

@rmacnak-google True, this indeed would be an even more robust approach. I think one of the original suggestions was to make TMP = LR to avoid blocking yet another register.

[sjindel-google]

Many places in the ARM assembler and compiler use IP directly rather than TMP.