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Merge pull request #9446 from Dentomologist/convert_shifttype_to_enum…
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Arm64Emitter: Convert ShiftType to enum class
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@lioncash
lioncash committed Jan 18, 2021
2 parents e62fa1e + e323766 commit 04ccd4c
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Showing 6 changed files with 105 additions and 77 deletions.
18 changes: 9 additions & 9 deletions Source/Core/Common/Arm64Emitter.cpp
View file
Expand Up @@ -1263,7 +1263,7 @@ void ARM64XEmitter::ISB(BarrierType type)
// Add/Subtract (extended register)
void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
ADD(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
ADD(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}

void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
Expand All @@ -1273,7 +1273,7 @@ void ARM64XEmitter::ADD(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Optio

void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EncodeArithmeticInst(0, true, Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
EncodeArithmeticInst(0, true, Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}

void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
Expand All @@ -1283,7 +1283,7 @@ void ARM64XEmitter::ADDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Opti

void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
SUB(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
SUB(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}

void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
Expand All @@ -1293,7 +1293,7 @@ void ARM64XEmitter::SUB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Optio

void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EncodeArithmeticInst(1, true, Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0));
EncodeArithmeticInst(1, true, Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}

void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
Expand All @@ -1303,7 +1303,7 @@ void ARM64XEmitter::SUBS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Opti

void ARM64XEmitter::CMN(ARM64Reg Rn, ARM64Reg Rm)
{
CMN(Rn, Rm, ArithOption(Rn, ST_LSL, 0));
CMN(Rn, Rm, ArithOption(Rn, ShiftType::LSL, 0));
}

void ARM64XEmitter::CMN(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
Expand All @@ -1313,7 +1313,7 @@ void ARM64XEmitter::CMN(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)

void ARM64XEmitter::CMP(ARM64Reg Rn, ARM64Reg Rm)
{
CMP(Rn, Rm, ArithOption(Rn, ST_LSL, 0));
CMP(Rn, Rm, ArithOption(Rn, ShiftType::LSL, 0));
}

void ARM64XEmitter::CMP(ARM64Reg Rn, ARM64Reg Rm, ArithOption Option)
Expand Down Expand Up @@ -1553,13 +1553,13 @@ void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift)
void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm)
{
if (IsGPR(Rd) && IsGPR(Rm))
ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_LSL, 0));
ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ShiftType::LSL, 0));
else
ASSERT_MSG(DYNA_REC, false, "Non-GPRs not supported in MOV");
}
void ARM64XEmitter::MVN(ARM64Reg Rd, ARM64Reg Rm)
{
ORN(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ST_LSL, 0));
ORN(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, ArithOption(Rm, ShiftType::LSL, 0));
}
void ARM64XEmitter::LSL(ARM64Reg Rd, ARM64Reg Rm, int shift)
{
Expand Down Expand Up @@ -2016,7 +2016,7 @@ void ARM64XEmitter::MOVI2R(ARM64Reg Rd, u64 imm, bool optimize)
// Max unsigned value (or if signed, -1)
// Set to ~ZR
ARM64Reg ZR = Is64Bit(Rd) ? SP : WSP;
ORN(Rd, ZR, ZR, ArithOption(ZR, ST_LSL, 0));
ORN(Rd, ZR, ZR, ArithOption(ZR, ShiftType::LSL, 0));
return;
}

Expand Down
58 changes: 43 additions & 15 deletions Source/Core/Common/Arm64Emitter.h
View file
Expand Up @@ -277,12 +277,16 @@ constexpr ARM64Reg EncodeRegToQuad(ARM64Reg reg)
return static_cast<ARM64Reg>(reg | 0xC0);
}

enum ShiftType
enum class ShiftType
{
ST_LSL = 0,
ST_LSR = 1,
ST_ASR = 2,
ST_ROR = 3,
// Logical Shift Left
LSL = 0,
// Logical Shift Right
LSR = 1,
// Arithmetic Shift Right
ASR = 2,
// Rotate Right
ROR = 3,
};

enum class IndexType
Expand Down Expand Up @@ -437,7 +441,7 @@ class ArithOption
m_width = WidthSpecifier::Width32Bit;
m_extend = ExtendSpecifier::UXTW;
}
m_shifttype = ST_LSL;
m_shifttype = ShiftType::LSL;
}
ArithOption(ARM64Reg Rd, ShiftType shift_type, u32 shift)
{
Expand Down Expand Up @@ -466,7 +470,7 @@ class ArithOption
case TypeSpecifier::ExtendedReg:
return (static_cast<u32>(m_extend) << 13) | (m_shift << 10);
case TypeSpecifier::ShiftedReg:
return (m_shifttype << 22) | (m_shift << 10);
return (static_cast<u32>(m_shifttype) << 22) | (m_shift << 10);
default:
DEBUG_ASSERT_MSG(DYNA_REC, false, "Invalid type in GetData");
break;
Expand Down Expand Up @@ -699,14 +703,38 @@ class ARM64XEmitter
void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);

// Wrap the above for saner syntax
void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { AND(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BIC(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORR(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORN(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EOR(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EON(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ANDS(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BICS(Rd, Rn, Rm, ArithOption(Rd, ST_LSL, 0)); }
void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
AND(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
BIC(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
ORR(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
ORN(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EOR(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
EON(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
ANDS(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
{
BICS(Rd, Rn, Rm, ArithOption(Rd, ShiftType::LSL, 0));
}
// Convenience wrappers around ORR. These match the official convenience syntax.
void MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift);
void MOV(ARM64Reg Rd, ARM64Reg Rm);
Expand Down
8 changes: 4 additions & 4 deletions Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
View file
Expand Up @@ -567,7 +567,7 @@ void JitArm64::rlwinmx(UGeckoInstruction inst)
{
ARM64Reg WA = gpr.GetReg();
MOVI2R(WA, mask);
AND(gpr.R(a), WA, gpr.R(s), ArithOption(gpr.R(s), ST_ROR, 32 - inst.SH));
AND(gpr.R(a), WA, gpr.R(s), ArithOption(gpr.R(s), ShiftType::ROR, 32 - inst.SH));
gpr.Unlock(WA);
}

Expand All @@ -592,7 +592,7 @@ void JitArm64::rlwnmx(UGeckoInstruction inst)
{
gpr.BindToRegister(a, a == s);
ARM64Reg WA = gpr.GetReg();
ArithOption Shift(gpr.R(s), ST_ROR, 32 - (gpr.GetImm(b) & 0x1f));
ArithOption Shift(gpr.R(s), ShiftType::ROR, 32 - (gpr.GetImm(b) & 0x1f));
MOVI2R(WA, mask);
AND(gpr.R(a), WA, gpr.R(s), Shift);
gpr.Unlock(WA);
Expand Down Expand Up @@ -656,7 +656,7 @@ void JitArm64::srawix(UGeckoInstruction inst)
if (a != s)
{
ASR(RA, RS, amount);
ANDS(dest, RA, RS, ArithOption(RS, ST_LSL, 32 - amount));
ANDS(dest, RA, RS, ArithOption(RS, ShiftType::LSL, 32 - amount));
}
else
{
Expand Down Expand Up @@ -1500,7 +1500,7 @@ void JitArm64::rlwimix(UGeckoInstruction inst)

MOVI2R(WA, mask);
BIC(WB, gpr.R(a), WA);
AND(WA, WA, gpr.R(s), ArithOption(gpr.R(s), ST_ROR, 32 - inst.SH));
AND(WA, WA, gpr.R(s), ArithOption(gpr.R(s), ShiftType::ROR, 32 - inst.SH));
ORR(gpr.R(a), WB, WA);

gpr.Unlock(WA, WB);
Expand Down
16 changes: 8 additions & 8 deletions Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
View file
Expand Up @@ -91,7 +91,7 @@ void JitArm64::mcrxr(UGeckoInstruction inst)
LDRB(IndexType::Unsigned, WB, PPC_REG, PPCSTATE_OFF(xer_so_ov));

// [0 SO OV CA]
ADD(WA, WA, WB, ArithOption(WB, ST_LSL, 2));
ADD(WA, WA, WB, ArithOption(WB, ShiftType::LSL, 2));
// [SO OV CA 0] << 3
LSL(WA, WA, 4);

Expand Down Expand Up @@ -136,7 +136,7 @@ void JitArm64::mfsrin(UGeckoInstruction inst)
ARM64Reg RB = gpr.R(b);

UBFM(index, RB, 28, 31);
ADD(index64, PPC_REG, index64, ArithOption(index64, ST_LSL, 2));
ADD(index64, PPC_REG, index64, ArithOption(index64, ShiftType::LSL, 2));
LDR(IndexType::Unsigned, gpr.R(d), index64, PPCSTATE_OFF(sr[0]));

gpr.Unlock(index);
Expand All @@ -155,7 +155,7 @@ void JitArm64::mtsrin(UGeckoInstruction inst)
ARM64Reg RB = gpr.R(b);

UBFM(index, RB, 28, 31);
ADD(index64, PPC_REG, index64, ArithOption(index64, ST_LSL, 2));
ADD(index64, PPC_REG, index64, ArithOption(index64, ShiftType::LSL, 2));
STR(IndexType::Unsigned, gpr.R(d), index64, PPCSTATE_OFF(sr[0]));

gpr.Unlock(index);
Expand Down Expand Up @@ -282,7 +282,7 @@ void JitArm64::mfspr(UGeckoInstruction inst)
ADD(XB, XB, 1);
UMULH(Xresult, Xresult, XB);

ADD(Xresult, XA, Xresult, ArithOption(Xresult, ST_LSR, 3));
ADD(Xresult, XA, Xresult, ArithOption(Xresult, ShiftType::LSR, 3));
STR(IndexType::Unsigned, Xresult, PPC_REG, PPCSTATE_OFF(spr[SPR_TL]));

if (CanMergeNextInstructions(1))
Expand Down Expand Up @@ -332,9 +332,9 @@ void JitArm64::mfspr(UGeckoInstruction inst)
ARM64Reg WA = gpr.GetReg();
LDRH(IndexType::Unsigned, RD, PPC_REG, PPCSTATE_OFF(xer_stringctrl));
LDRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_ca));
ORR(RD, RD, WA, ArithOption(WA, ST_LSL, XER_CA_SHIFT));
ORR(RD, RD, WA, ArithOption(WA, ShiftType::LSL, XER_CA_SHIFT));
LDRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_so_ov));
ORR(RD, RD, WA, ArithOption(WA, ST_LSL, XER_OV_SHIFT));
ORR(RD, RD, WA, ArithOption(WA, ShiftType::LSL, XER_OV_SHIFT));
gpr.Unlock(WA);
}
break;
Expand Down Expand Up @@ -633,7 +633,7 @@ void JitArm64::mfcr(UGeckoInstruction inst)
else
{
UBFX(XC, CR, 61, 1);
ORR(XA, XC, XA, ArithOption(XA, ST_LSL, 4));
ORR(XA, XC, XA, ArithOption(XA, ShiftType::LSL, 4));
}

// EQ
Expand All @@ -648,7 +648,7 @@ void JitArm64::mfcr(UGeckoInstruction inst)

// LT
UBFX(XC, CR, 62, 1);
ORR(WA, WA, WC, ArithOption(WC, ST_LSL, 3));
ORR(WA, WA, WC, ArithOption(WC, ShiftType::LSL, 3));
}

gpr.Unlock(WC);
Expand Down

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