PowerPC: Implement broken masking for uncached unaligned writes #9964
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The code for raising the interrupt doesn't seem to be working properly, at least not when running my hardware test. But everything else should be working. |
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The actual build works!!!! (with AlignmentQuirks = True) |
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How much performance would it cost to enable this feature by default? If the cost is low (less than 1% in most games) it might be worth enabling it by default. Do games even do that many uncached writes by default? |
Don't forget segher who spent like 4h explaining to me how the 60x bus works on IRC :-) |
@JMC47, would you like to test? (My laptop with its thermal throttling is probably not the best for testing small performance differences) Something I want to note is that I plan to revive and fix PR #9865 at some point after this PR has been merged, and I think it would be natural to put the behavior implemented in that PR under the same |
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After some discussion and some quick testing of how often games access uncached memory (100-1000 reads per frame and essentially no writes, it seems like), I've decided to remove the setting for now. Uncached reads and writes will now always go through slowmem. |
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Seems like everyone is in agreement. Just be sure to watch this for potential performance regressions down the line. |
One of the following commits will add emulation of a quirk that only happens when writing to memory which is mapped as write-through or cache-inhibited, so let's keep track of which memory is mapped in this way.
Write_U16_Swap leaves the upper 32 bits alone. Reimplementing this correctly in the JIT would require more than one instruction, so let's just call Write_U16_Swap instead, like Jit64 does.
This implements the behavior described in https://bugs.dolphin-emu.org/issues/12565. Thank you to eigenform, delroth, phire, marcan, segher, and Extrems for all helping in one way or another with the efforts to reverse engineer this behavior, and to Rylie for reporting the issue.
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Noticed a typo in the third commit message just now, in case anyone finds this in the future and wonders about it. It should say "upper 16 bits" instead of "upper 32 bits". |
This implements the behavior described in https://bugs.dolphin-emu.org/issues/12565.
The implementation requires writes to pass through slowmem in order to be affected. Since most users probably don't care about emulating this behavior and thus wouldn't want performance to get lower just for the sake of emulating it, I've added a new INI-only setting
AlignmentQuirkswhich controls whether slowmem is forced for uncached memory.Thank you to eigenform, delroth, phire, marcan, segher, and Extrems for all helping in one way or another with the efforts to reverse engineer this behavior, and to Rylie for reporting the issue.