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Optimization on LinearScan::buildPhysRegRecords #83862

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merged 3 commits into from
Apr 1, 2023

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Ruihan-Yin
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@Ruihan-Yin Ruihan-Yin commented Mar 23, 2023

introducing separate macro on upper 16 zmm registers and lower 16 zmm registers, skipping upper 16 registers unless on 64-bit system.

@ghost ghost added the community-contribution Indicates that the PR has been added by a community member label Mar 23, 2023
@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Mar 23, 2023
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ghost commented Mar 23, 2023

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch, @kunalspathak
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Issue Details

introducing separate macro on higher 16 zmm registers and lower 16 zmm registers, skipping non-AVX512 register if AVX512 not available.

Author: Ruihan-Yin
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area-CodeGen-coreclr, community-contribution

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@Ruihan-Yin
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@dotnet-policy-service agree company="Intel Corporation"

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some tests failed, but it seems not to be caused by the changes in this PR.

@Ruihan-Yin Ruihan-Yin marked this pull request as ready for review March 27, 2023 23:16
@tannergooding
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Failure is unrelated and being handled by #84012

fix the offset value when allocating upper registers, it should
be the length of the lower register group.
@Ruihan-Yin
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@tannergooding Hi, is there anything further we need to do? Or this PR is ready to be merged.

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@kunalspathak kunalspathak left a comment

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LGTM

It seems the TP regression shows up because helix machines has EVEX encoding and this PR adds the extra check for it? @tannergooding - is that the right conclusion?

image

@kunalspathak kunalspathak merged commit d6455cb into dotnet:main Apr 1, 2023
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Thanks all!

@ghost ghost locked as resolved and limited conversation to collaborators May 3, 2023
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3 participants