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VHDL calling graph doesn't work as expected (Origin: bugzilla #600940) #3576

doxygen opened this Issue Jul 2, 2018 · 0 comments


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doxygen commented Jul 2, 2018

status RESOLVED severity minor in component general for ---
Reported in version 1.6.1 on platform Other
Assigned to: Dimitri van Heesch

On 2009-11-06 10:12:25 +0000, Steffen Jaeckel wrote:

When an entity instantiates another entity it won't be displayed in the calling graph.

A short example would be


entity ent1 is
port ( signal sig1 : out std_logic );
end ent1;
architecture ent1_arch of ent1 is
end ent1_arch;


entity ent2 is
end ent2;
architecture ent2_arch of ent2 is
component ent1 is
port ( signal sig1 : out std_logic );
end component
signal ent1_sig1 : std_logic;
ent1_instance: ent1
port map ( sig1 => ent1_sig1 );
end ent2_arch;

On 2009-11-07 09:44:18 +0000, mk wrote:

check out release Doxygen-1.6.1-20091027 and the calling graph should work

On 2009-12-30 13:38:49 +0000, Dimitri van Heesch wrote:

This bug was previously marked ASSIGNED, which means it should be fixed in
doxygen version 1.6.2. Please verify if this is indeed the case and reopen the
bug if you think it is not fixed (include any additional information that you
think can be relevant).

@doxygen doxygen closed this Jul 2, 2018

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