Feature: Add verilator support

[dpretet]

While writing a SystemVerilog based IP, Verilator became a very important feature to implement.
feature-verilator branch start to put in place this simulator support.

[dpretet]

After evaluation of Verilator, the tool can't integrated to SVUT because of its non-support of wait, @ EVENT or delay statements. The branch will merge to master nonetheless because it brings many code clean-up and simplification.

• Macros have been cleaned and unified when possible
• Macros share a common message format with a dedicated function
• It's now possible to pass an expression to evaluate to a macro.