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Extra 0xff byte on SPI when using cs other than 0 #47
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Well, this is an old piece of code that definitely needs some improvement, I hope there is a better solution than the current implementation. Let me check if I can fix this properly. |
Could you give a try to |
I have no idea how to do that. |
Somehow i closed this. Not my intention... |
I've rewritten pyftdi.spi
|
The best solution would be to create a pull request, or to attach a patch file. |
Extra useless bytes should have been fixed with v0.23.0 (a42e83b) |
SPI mode 0, 1, 3 implemented. |
Would it be ok if i send it to emmanuel.blot@free.fr? |
If it is easier for you, yes, go ahead. Thanks. |
i've send you the code. Unfortunately our EMail-Provider is pretty much down due to DDos, please tell me wheter you got the Mail |
Hello!
First of all thanks for this great lib.
I'm using it to interface a FPGA via a FTDI4232 SPI on interface 2. It works
great, however if i use CS 1 or 2 i see an extra 8 1 Bits clocked in before CS goes up.
It is not a real problem, because i can just ignore that byte. But i'm wondering
nevertheless...
I've checked the pyftdi.spi code to the limited extend of my capabilities.
This is what i believe it does, when writing:
-- ftdi.WRITE_BITS_TMS_NVE (line 153)
-- pulling up all outputs (line 155)
I am wondering wheter line 153 might be a problem. I believe it pulls up the
TMS/CS-pin for eight clock cycles, while still emitting said clock cycles, however
my application does not use the default CS, which would be 0, but another one,
and thus clocks out eight additional bits.
I've commented line 153 and the eight bits are gone.
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