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Extra 0xff byte on SPI when using cs other than 0 #47

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vloewis opened this issue May 17, 2017 · 11 comments
Closed

Extra 0xff byte on SPI when using cs other than 0 #47

vloewis opened this issue May 17, 2017 · 11 comments

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@vloewis
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vloewis commented May 17, 2017

Hello!
First of all thanks for this great lib.
I'm using it to interface a FPGA via a FTDI4232 SPI on interface 2. It works
great, however if i use CS 1 or 2 i see an extra 8 1 Bits clocked in before CS goes up.
It is not a real problem, because i can just ignore that byte. But i'm wondering
nevertheless...
I've checked the pyftdi.spi code to the limited extend of my capabilities.
This is what i believe it does, when writing:

  • A byte sequence containing the MPSSE codes and the data is assembled
  • The sequence starts with setting SCLK, MOSI and the selected CS to low (line 189)
  • Next comes the data transmission command including data (line 236)
  • If turbo == True and complete == True and silent_clock == False, the sequence finishes with
    -- ftdi.WRITE_BITS_TMS_NVE (line 153)
    -- pulling up all outputs (line 155)

I am wondering wheter line 153 might be a problem. I believe it pulls up the
TMS/CS-pin for eight clock cycles, while still emitting said clock cycles, however
my application does not use the default CS, which would be 0, but another one,
and thus clocks out eight additional bits.


I've commented line 153 and the eight bits are gone.

@eblot
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eblot commented May 18, 2017

Well, this is an old piece of code that definitely needs some improvement, I hope there is a better solution than the current implementation. Let me check if I can fix this properly.

@eblot
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eblot commented May 19, 2017

Could you give a try to spi-cs-fix branch?

@vloewis
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vloewis commented May 22, 2017

Could you give a try to spi-cs-fix branch?

I have no idea how to do that.

@vloewis vloewis closed this as completed May 22, 2017
@vloewis
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vloewis commented May 22, 2017

Somehow i closed this. Not my intention...
I'll give it a shot.

@vloewis vloewis reopened this May 22, 2017
@vloewis
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vloewis commented May 23, 2017

I've rewritten pyftdi.spi

  • plus modes
  • plus duplex
    Do you mind if i send it to you? If not whereto?

@eblot
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eblot commented Jun 6, 2017

The best solution would be to create a pull request, or to attach a patch file.

@eblot
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eblot commented Jun 10, 2017

Extra useless bytes should have been fixed with v0.23.0 (a42e83b)

@eblot
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eblot commented Jun 12, 2017

SPI mode 0, 1, 3 implemented.
If you known a workaround for mode 2, I would be interested with your implementation.

@vloewis
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vloewis commented Jun 12, 2017

Would it be ok if i send it to emmanuel.blot@free.fr?

@eblot
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eblot commented Jun 12, 2017

If it is easier for you, yes, go ahead. Thanks.

@vloewis vloewis closed this as completed Jun 13, 2017
@vloewis vloewis reopened this Jun 13, 2017
@vloewis
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vloewis commented Jun 13, 2017

i've send you the code. Unfortunately our EMail-Provider is pretty much down due to DDos, please tell me wheter you got the Mail

@vloewis vloewis closed this as completed Jun 13, 2017
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