Replace uses of TR::comp() with cheaper alternatives

The `TR::Compilation` object is sometimes fetched from TLS (via `TR::comp()`)
when there are cheaper alternative means available (e.g., fetching it from
a `TR::CodeGenerator` object).  Replace some obvious candidates.  Also,
when the TLS version must be used, optimize its use to avoid repeated calls
in the same method.

Signed-off-by: Daryl Maier <maier@ca.ibm.com>

compiler/arm/codegen/OMRInstruction.cpp

@@ -135,7 +135,7 @@ OMR::ARM::Instruction::Instruction(TR::Instruction                     *precedin
 
 void OMR::ARM::Instruction::ARMNeedsGCMap(uint32_t mask)
    {
-   if (TR::comp()->useRegisterMaps())
+   if (self()->cg()->comp()->useRegisterMaps())
       self()->setNeedsGCMap(mask);
    }
 
@@ -303,7 +303,7 @@ TR::ARMImmSymInstruction::ARMImmSymInstruction(TR::Instruction
 
 void TR::ARMLabelInstruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
    {
-   TR::Compilation *comp = TR::comp();
+   TR::Compilation *comp = cg()->comp();
    TR::Machine  *machine        = cg()->machine();
    TR::Register    *target1Virtual = getTarget1Register();
    TR::Register    *source1Virtual = getSource1Register();

compiler/optimizer/InductionVariable.cpp

@@ -3992,8 +3992,9 @@ static void orderSensitiveDescendants(TR::Node *node, TR::NodeChecklist &out)
  */
 static bool substPreservesEvalOrder(TR::Node *orig, TR::Node *replacement)
    {
-   TR::NodeChecklist origEvaluated(TR::comp());
-   TR::NodeChecklist replacementEvaluated(TR::comp());
+   TR::Compilation *comp = TR::comp();
+   TR::NodeChecklist origEvaluated(comp);
+   TR::NodeChecklist replacementEvaluated(comp);
    orderSensitiveDescendants(orig, origEvaluated);
    orderSensitiveDescendants(replacement, replacementEvaluated);
    return origEvaluated == replacementEvaluated;

compiler/optimizer/LocalOpts.cpp

@@ -2288,7 +2288,7 @@ bool TR_CompactNullChecks::replaceNullCheckIfPossible(TR::Node *cursorNode, TR::
       if (isEquivalent)
          {
          bool canBeRemoved = true; //comp()->cg()->canNullChkBeImplicit(cursorNode);
-         if (TR::comp()->getOption(TR_DisableTraps) ||
+         if (comp()->getOption(TR_DisableTraps) ||
              TR::Compiler->om.offsetOfObjectVftField() >= comp()->cg()->getNumberBytesReadInaccessible())
            canBeRemoved = false;
 

compiler/optimizer/LoopReplicator.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2020 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -67,11 +67,13 @@ TR_LoopReplicator::TR_LoopReplicator(TR::OptimizationManager *manager)
 //Add static debug counter for a given replication failure
 static void countReplicationFailure(char *failureReason, int32_t regionNum)
    {
+   TR::Compilation *comp = TR::comp();
+
    //Assemble format string: "LoopReplicator/<failureReason>/%s/(%s)/region_%d"
-   TR::DebugCounter::incStaticDebugCounter(TR::comp(), TR::DebugCounter::debugCounterName(TR::comp(),
+   TR::DebugCounter::incStaticDebugCounter(comp, TR::DebugCounter::debugCounterName(comp,
       "LoopReplicator/%s/%s/(%s)/region_%d", failureReason,
-      TR::comp()->getHotnessName(TR::comp()->getMethodHotness()),
-      TR::comp()->signature(), regionNum));
+      comp->getHotnessName(comp->getMethodHotness()),
+      comp->signature(), regionNum));
    }
 
 int32_t TR_LoopReplicator::perform()

compiler/optimizer/VirtualGuardHeadMerger.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2020 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -183,11 +183,11 @@ static void collectDirectLoads(TR::Node *node, TR_BitVector &loadSymRefs, TR::No
  * @param firstBlock The guard's branch destination
  * @param coldPathLoads BitVector of symbol reference numbers for any direct loads seen until the merge back to mainline
  */
-static void collectColdPathLoads(TR::Block* firstBlock, TR_BitVector &coldPathLoads)
+static void collectColdPathLoads(TR::Block* firstBlock, TR_BitVector &coldPathLoads, TR::Compilation *comp)
    {
-   TR_Stack<TR::Block*> blocksToCheck(TR::comp()->trMemory(), 8, false, stackAlloc);
+   TR_Stack<TR::Block*> blocksToCheck(comp->trMemory(), 8, false, stackAlloc);
    blocksToCheck.push(firstBlock);
-   TR::NodeChecklist checklist(TR::comp());
+   TR::NodeChecklist checklist(comp);
 
    coldPathLoads.empty();
    while (!blocksToCheck.isEmpty())
@@ -201,17 +201,17 @@ static void collectColdPathLoads(TR::Block* firstBlock, TR_BitVector &coldPathLo
       for (auto itr = block->getSuccessors().begin(), end = block->getSuccessors().end(); itr != end; ++itr)
          {
          TR::Block *dest = (*itr)->getTo()->asBlock();
-         if (dest != TR::comp()->getFlowGraph()->getEnd() && dest->getPredecessors().size() == 1)
+         if (dest != comp->getFlowGraph()->getEnd() && dest->getPredecessors().size() == 1)
             blocksToCheck.push(dest);
          }
       }
    }
 
 static bool safeToMoveGuard(TR::Block *destination, TR::TreeTop *guardCandidate,
-   TR::TreeTop *branchDest, TR_BitVector &privArgSymRefs)
+   TR::TreeTop *branchDest, TR_BitVector &privArgSymRefs, TR::Compilation *comp)
    {
    static char *disablePrivArgMovement = feGetEnv("TR_DisableRuntimeGuardPrivArgMovement");
-   TR::TreeTop *start = destination ? destination->getExit() : TR::comp()->getStartTree();
+   TR::TreeTop *start = destination ? destination->getExit() : comp->getStartTree();
    if (guardCandidate->getNode()->isHCRGuard())
       {
       for (TR::TreeTop *tt = start; tt && tt != guardCandidate; tt = tt->getNextTreeTop())
@@ -224,7 +224,7 @@ static bool safeToMoveGuard(TR::Block *destination, TR::TreeTop *guardCandidate,
       {
       for (TR::TreeTop *tt = start; tt && tt != guardCandidate; tt = tt->getNextTreeTop())
          {
-         if (TR::comp()->isPotentialOSRPoint(tt->getNode(), NULL, true))
+         if (comp->isPotentialOSRPoint(tt->getNode(), NULL, true))
             return false;
          }
       }
@@ -247,7 +247,7 @@ static bool safeToMoveGuard(TR::Block *destination, TR::TreeTop *guardCandidate,
              (guardCandidate->getNode()->getInlinedSiteIndex() > -1 &&
              // if priv arg store does not have the same inlined site index as the guard's caller, that means it is not a priv arg for this guard,
              // then we cannot move the guard and its priv args up across other calls' priv args
-             tt->getNode()->getInlinedSiteIndex() != TR::comp()->getInlinedCallSite(guardCandidate->getNode()->getInlinedSiteIndex())._byteCodeInfo.getCallerIndex())))
+             tt->getNode()->getInlinedSiteIndex() != comp->getInlinedCallSite(guardCandidate->getNode()->getInlinedSiteIndex())._byteCodeInfo.getCallerIndex())))
             return false;
 
          if (tt->getNode()->chkIsPrivatizedInlinerArg())
@@ -263,7 +263,6 @@ static bool safeToMoveGuard(TR::Block *destination, TR::TreeTop *guardCandidate,
 
 static void moveBlockAfterDest(TR::CFG *cfg, TR::Block *toMove, TR::Block *dest)
    {
-   TR::Compilation *comp = TR::comp();
    // Step1 splice out toMove
    TR::Block *toMovePrev = toMove->getPrevBlock();
    TR::Block *toMoveSucc = toMove->getNextBlock();
@@ -411,7 +410,7 @@ int32_t TR_VirtualGuardHeadMerger::perform() {
                break;
 
             TR::Block *insertPoint = isStopTheWorldGuard(guard2) ? HCRIns : runtimeIns;
-            if (!safeToMoveGuard(insertPoint, guard2Tree, guard1->getBranchDestination(), privArgSymRefs))
+            if (!safeToMoveGuard(insertPoint, guard2Tree, guard1->getBranchDestination(), privArgSymRefs, comp()))
                break;
 
             // now we figure out if we can redirect guard2 to guard1's cold block
@@ -423,7 +422,7 @@ int32_t TR_VirtualGuardHeadMerger::perform() {
                   traceMsg(comp(), "  Guard1 [%p] is guarding the same call as Guard2 [%p] - proceeding with guard merging\n", guard1, guard2);
                }
             else if (guard2->getInlinedSiteIndex() > -1 &&
-                guard1->getInlinedSiteIndex() == TR::comp()->getInlinedCallSite(guard2->getInlinedSiteIndex())._byteCodeInfo.getCallerIndex())
+                guard1->getInlinedSiteIndex() == comp()->getInlinedCallSite(guard2->getInlinedSiteIndex())._byteCodeInfo.getCallerIndex())
                {
                if (trace())
                   traceMsg(comp(), "  Guard1 [%p] is the caller of Guard2 [%p] - proceeding with guard merging\n", guard1, guard2);
@@ -450,7 +449,7 @@ int32_t TR_VirtualGuardHeadMerger::perform() {
                {
                if (!evaluatedColdPathLoads)
                   {
-                  collectColdPathLoads(cold1, coldPathLoads);
+                  collectColdPathLoads(cold1, coldPathLoads, comp());
                   evaluatedColdPathLoads = true;
                   }
 

compiler/p/codegen/OMRInstruction.cpp

@@ -78,7 +78,7 @@ OMR::Power::Instruction::isCall()
 void
 OMR::Power::Instruction::PPCNeedsGCMap(uint32_t mask)
    {
-   if (TR::comp()->useRegisterMaps())
+   if (self()->cg()->comp()->useRegisterMaps())
       self()->setNeedsGCMap(mask);
    }
 

compiler/p/codegen/PPCInstruction.hpp

@@ -1236,7 +1236,7 @@ class PPCMemInstruction : public TR::Instruction
 
    virtual TR::Register *getMemoryBase()    {return getMemoryReference()->getBaseRegister();}
    virtual TR::Register *getMemoryIndex()   {return getMemoryReference()->getIndexRegister();}
-   virtual int64_t      getOffset()        {return getMemoryReference()->getOffset(*TR::comp());}
+   virtual int64_t      getOffset()        {return getMemoryReference()->getOffset(*(cg()->comp()));}
 
    virtual void fillBinaryEncodingFields(uint32_t *cursor);
    virtual TR::Instruction *expandInstruction();
@@ -1384,7 +1384,7 @@ class PPCTrg1MemInstruction : public PPCTrg1Instruction
 
    virtual TR::Register *getMemoryBase()    {return getMemoryReference()->getBaseRegister();}
    virtual TR::Register *getMemoryIndex()   {return getMemoryReference()->getIndexRegister();}
-   virtual int64_t      getOffset()        {return getMemoryReference()->getOffset(*TR::comp());}
+   virtual int64_t      getOffset()        {return getMemoryReference()->getOffset(*(cg()->comp()));}
 
    bool encodeMutexHint();
    bool haveHint() {return getHint() != PPCOpProp_NoHint;};

compiler/x/codegen/BinaryCommutativeAnalyser.cpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2020 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -74,14 +74,14 @@ zeroExtendTo32BitRegister(TR::Node          *node,
    }
 
 /*
- * \brief 
- * this API is for check nodes(like OverflowCHK) with certain operation where the operands 
+ * \brief
+ * this API is for check nodes(like OverflowCHK) with certain operation where the operands
  * are given explicitly by the caller and are not the first and second child of the given root node
  *
  * \param root
  *     the check node
- * \param firstChild, secondChild 
- *     the operands for the operation 
+ * \param firstChild, secondChild
+ *     the operands for the operation
  */
 void TR_X86BinaryCommutativeAnalyser::genericAnalyserWithExplicitOperands(TR::Node      *root,
                                                                           TR::Node      *firstChild,
@@ -99,7 +99,7 @@ void TR_X86BinaryCommutativeAnalyser::genericAnalyserWithExplicitOperands(TR::No
    }
 
 /*
- * \brief 
+ * \brief
  * this API is for regular operation nodes where the first child and second child are the operands by default
  */
 void TR_X86BinaryCommutativeAnalyser::genericAnalyser(TR::Node      *root,
@@ -130,7 +130,7 @@ void TR_X86BinaryCommutativeAnalyser::genericAnalyser(TR::Node      *root,
    }
 
 /*
- * users should call the genericAnalyser or genericAnalyserWithExplicitOperands APIs instead of calling this one directly 
+ * users should call the genericAnalyser or genericAnalyserWithExplicitOperands APIs instead of calling this one directly
  */
 TR::Register* TR_X86BinaryCommutativeAnalyser::genericAnalyserImpl(TR::Node      *root,
                                                                    TR::Node      *firstChild,
@@ -700,7 +700,7 @@ void TR_X86BinaryCommutativeAnalyser::genericLongAnalyser(TR::Node       *root,
    }
 
 /*
- * \brief 
+ * \brief
  * this API is intended for regular add operation nodes where the first child and second child are the operands by default
  */
 void TR_X86BinaryCommutativeAnalyser::integerAddAnalyser(TR::Node      *root,
@@ -731,18 +731,18 @@ void TR_X86BinaryCommutativeAnalyser::integerAddAnalyser(TR::Node      *root,
    }
 
 /*
- * \brief 
- * this API is for check nodes(like OverflowCHK) with an add operation where the operands 
+ * \brief
+ * this API is for check nodes(like OverflowCHK) with an add operation where the operands
  * are given explicitly by the caller and are not the first and second child of the given root node
  *
  * \param root
  *     the check node
- * \param firstChild, secondChild 
- *     the operands for the add operation 
+ * \param firstChild, secondChild
+ *     the operands for the add operation
  */
 void TR_X86BinaryCommutativeAnalyser::integerAddAnalyserWithExplicitOperands(TR::Node      *root,
-                                                                             TR::Node      *firstChild, 
-                                                                             TR::Node      *secondChild, 
+                                                                             TR::Node      *firstChild,
+                                                                             TR::Node      *secondChild,
                                                                              TR_X86OpCodes regRegOpCode,
                                                                              TR_X86OpCodes regMemOpCode,
                                                                              bool          needsEflags, // false by default
@@ -754,16 +754,16 @@ void TR_X86BinaryCommutativeAnalyser::integerAddAnalyserWithExplicitOperands(TR:
    _cg->decReferenceCount(secondChild);
    _cg->stopUsingRegister(tempReg);
    }
- 
+
 /*
- * users should call the integerAddAnalyser or integerAddAnalyserWithGivenOperands APIs instead of calling this one directly 
+ * users should call the integerAddAnalyser or integerAddAnalyserWithGivenOperands APIs instead of calling this one directly
  */
 TR::Register *TR_X86BinaryCommutativeAnalyser::integerAddAnalyserImpl(TR::Node      *root,
-                                                                      TR::Node      *firstChild, 
-                                                                      TR::Node      *secondChild, 
+                                                                      TR::Node      *firstChild,
+                                                                      TR::Node      *secondChild,
                                                                       TR_X86OpCodes regRegOpCode,
                                                                       TR_X86OpCodes regMemOpCode,
-                                                                      bool          needsEflags,     
+                                                                      bool          needsEflags,
                                                                       TR::Node      *carry)
    {
    TR::Register *targetRegister;
@@ -927,9 +927,9 @@ TR::Register *TR_X86BinaryCommutativeAnalyser::integerAddAnalyserImpl(TR::Node
 // get clobbered by the memory barrier immediately preceding the
 // ADC4RegMem instruction.
 //
-static bool isVolatileMemoryOperand(TR::Node *node)
+bool TR_X86BinaryCommutativeAnalyser::isVolatileMemoryOperand(TR::Node *node)
    {
-   TR::Compilation *comp = TR::comp();
+   TR::Compilation *comp = _cg->comp();
    TR_ASSERT_FATAL(comp, "isVolatileMemoryOperand should only be called during a compilation!");
    if (comp->target().isSMP() && node->getOpCode().isMemoryReference())
       {
@@ -941,14 +941,14 @@ static bool isVolatileMemoryOperand(TR::Node *node)
    }
 
 /*
- * \brief 
- * this API is for check nodes(like OverflowCHK) an ladd operation where the operands 
+ * \brief
+ * this API is for check nodes(like OverflowCHK) an ladd operation where the operands
  * are given explicitly by the caller and are not the first and second child of the given root node
  *
  * \param root
  *     the check node
- * \param firstChild, secondChild 
- *     the operands for the add operation 
+ * \param firstChild, secondChild
+ *     the operands for the add operation
  */
 void TR_X86BinaryCommutativeAnalyser::longAddAnalyserWithExplicitOperands(TR::Node *root, TR::Node *firstChild, TR::Node *secondChild)
    {
@@ -960,12 +960,12 @@ void TR_X86BinaryCommutativeAnalyser::longAddAnalyserWithExplicitOperands(TR::No
    }
 
 /*
- * \brief 
+ * \brief
  * this API is intended for regular ladd operation nodes where the first child and second child are the operands by default
  */
 void TR_X86BinaryCommutativeAnalyser::longAddAnalyser(TR::Node *root)
    {
-   TR::Node *firstChild = NULL; 
+   TR::Node *firstChild = NULL;
    TR::Node *secondChild = NULL;
    if (_cg->whichChildToEvaluate(root) == 0)
       {
@@ -986,7 +986,7 @@ void TR_X86BinaryCommutativeAnalyser::longAddAnalyser(TR::Node *root)
    }
 
 /*
- * users should call the longAddAnalyser or longAddAnalyserWithExplicitOperands APIs instead of calling this one directly 
+ * users should call the longAddAnalyser or longAddAnalyserWithExplicitOperands APIs instead of calling this one directly
  */
 TR::Register* TR_X86BinaryCommutativeAnalyser::longAddAnalyserImpl(TR::Node *root, TR::Node *&firstChild, TR::Node *&secondChild)
    {

compiler/x/codegen/BinaryCommutativeAnalyser.hpp

@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2020 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -96,15 +96,15 @@ class TR_X86BinaryCommutativeAnalyser  : public TR_Analyser
                                                TR::Node *secondChild,
                                                TR_X86OpCodes regRegOpCode,
                                                TR_X86OpCodes regMemOpCode,
-                                               bool needsEflags = false, 
+                                               bool needsEflags = false,
                                                TR::Node *carry = 0);
 
    TR::Register* integerAddAnalyserImpl(TR::Node       *root,
                            TR::Node *firstChild,
                            TR::Node *secondChild,
                            TR_X86OpCodes regRegOpCode,
                            TR_X86OpCodes regMemOpCode,
-                           bool needsEflags, 
+                           bool needsEflags,
                            TR::Node *carry);
 
    void longAddAnalyserWithExplicitOperands(TR::Node *root, TR::Node *firstChild, TR::Node *secondChild);
@@ -128,6 +128,7 @@ class TR_X86BinaryCommutativeAnalyser  : public TR_Analyser
    bool getOpReg2Mem1() {return (_actionMap[getInputs()] & OpReg2Mem1) ? true : false;}
    bool getCopyRegs()   {return (_actionMap[getInputs()] & (CopyReg1 | CopyReg2)) ? true : false;}
 
+   bool isVolatileMemoryOperand(TR::Node *node);
    };
 
 #endif

compiler/x/codegen/OMRCodeGenerator.cpp

@@ -232,7 +232,7 @@ OMR::X86::CodeGenerator::initialize(TR::Compilation *comp)
 
 #if defined(TR_TARGET_X86) && !defined(J9HAMMER)
    TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) == _targetProcessorInfo.supportsSSE2(), "supportsSSE2() failed\n");
-   
+
    if (comp->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) && comp->target().cpu.testOSForSSESupport())
       supportsSSE2 = true;
 #endif // defined(TR_TARGET_X86) && !defined(J9HAMMER)
@@ -2927,7 +2927,7 @@ TR_X86ScratchRegisterManager *OMR::X86::CodeGenerator::generateScratchRegisterMa
 bool
 TR_X86ScratchRegisterManager::reclaimAddressRegister(TR::MemoryReference *mr)
    {
-   if (TR::comp()->target().is32Bit())
+   if (_cg->comp()->target().is32Bit())
       return false;
 
    return reclaimScratchRegister(mr->getAddressRegister());