Add x87 instructions intended for use with pre-encoded registers.

Laying groundwork for removal of x87. See #946 Signed-off-by: BradleyWood <bradley.wood@ibm.com>
eclipse · Jun 9, 2021 · 059eeca · 059eeca
1 parent b173e31
commit 059eeca
Show file tree

Hide file tree

Showing 3 changed files with 18 additions and 0 deletions.
diff --git a/compiler/x/codegen/OMRInstOpCode.enum b/compiler/x/codegen/OMRInstOpCode.enum
@@ -303,13 +303,15 @@
    FISTPMem,
    DISTPMem,
    FLSTPMem,
+   FLSTTPMem,
    DLSTPMem,
    FSSTMemReg,
    DSSTMemReg,
    FSSTPMem,
    DSSTPMem,
    FLDLN2,
    FLDRegReg,
+   FLDDUP,
    DLDRegReg,
    FLDRegMem,
    DLDRegMem,
@@ -339,6 +341,7 @@
    FSTPMemReg,
    DSTPMemReg,
    FSTPReg,
+   FSTPST0,
    DSTPReg,
    STCWMem,
    STSWMem,

diff --git a/compiler/x/codegen/OMRInstOpCode.enum.temp.defines b/compiler/x/codegen/OMRInstOpCode.enum.temp.defines
@@ -296,13 +296,15 @@
 #define   FISTPMem OMR::InstOpCode::FISTPMem
 #define   DISTPMem OMR::InstOpCode::DISTPMem
 #define   FLSTPMem OMR::InstOpCode::FLSTPMem
+#define   FLSTTPMem OMR::InstOpCode::FLSTTPMem
 #define   DLSTPMem OMR::InstOpCode::DLSTPMem
 #define   FSSTMemReg OMR::InstOpCode::FSSTMemReg
 #define   DSSTMemReg OMR::InstOpCode::DSSTMemReg
 #define   FSSTPMem OMR::InstOpCode::FSSTPMem
 #define   DSSTPMem OMR::InstOpCode::DSSTPMem
 #define   FLDLN2 OMR::InstOpCode::FLDLN2
 #define   FLDRegReg OMR::InstOpCode::FLDRegReg
+#define   FLDDUP OMR::InstOpCode::FLDDUP
 #define   DLDRegReg OMR::InstOpCode::DLDRegReg
 #define   FLDRegMem OMR::InstOpCode::FLDRegMem
 #define   DLDRegMem OMR::InstOpCode::DLDRegMem
@@ -332,6 +334,7 @@
 #define   FSTPMemReg OMR::InstOpCode::FSTPMemReg
 #define   DSTPMemReg OMR::InstOpCode::DSTPMemReg
 #define   FSTPReg OMR::InstOpCode::FSTPReg
+#define   FSTPST0 OMR::InstOpCode::FSTPST0
 #define   DSTPReg OMR::InstOpCode::DSTPReg
 #define   STCWMem OMR::InstOpCode::STCWMem
 #define   STSWMem OMR::InstOpCode::STSWMem

diff --git a/compiler/x/codegen/X86Ops.ins b/compiler/x/codegen/X86Ops.ins
@@ -1155,6 +1155,10 @@ INSTRUCTION(FLSTPMem, flstp,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xdf, X87_________________(0x38)),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IsPopInstruction | IA32OpProp_SingleFP),
             PROPERTY1(IA32OpProp1_SourceIsMemRef)),
+INSTRUCTION(FLSTTPMem, flsttp,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xdd, X87_________________(0x08)),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IsPopInstruction | IA32OpProp_SingleFP),
+            PROPERTY1(IA32OpProp1_SourceIsMemRef)),
 INSTRUCTION(DLSTPMem, flstp,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xdf, X87_________________(0x38)),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IsPopInstruction | IA32OpProp_DoubleFP),
@@ -1183,6 +1187,10 @@ INSTRUCTION(FLDRegReg, fld,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xd9, X87_________________(0xc0)),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SingleFP),
             PROPERTY1(IA32OpProp1_TargetRegIsImplicit)),
+INSTRUCTION(FLDDUP, fld,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xd9, X87_________________(0xc0)),
+            PROPERTY0(IA32OpProp_ModifiesTarget),
+            PROPERTY1(IA32OpProp1_TargetRegIsImplicit | IA32OpProp1_SourceRegIsImplicit)),
 INSTRUCTION(DLDRegReg, fld,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xd9, X87_________________(0xc0)),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_DoubleFP),
@@ -1299,6 +1307,10 @@ INSTRUCTION(FSTPReg, fstp,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xdd, X87_________________(0xd8)),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IsPopInstruction | IA32OpProp_SingleFP),
             PROPERTY1(IA32OpProp1_SourceRegIsImplicit)),
+INSTRUCTION(FSTPST0, fstp,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xdd, X87_________________(0xd8)),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IsPopInstruction | IA32OpProp_SingleFP),
+            PROPERTY1(IA32OpProp1_TargetRegIsImplicit | IA32OpProp1_SourceRegIsImplicit)),
 INSTRUCTION(DSTPReg, fstp,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0xdd, X87_________________(0xd8)),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IsPopInstruction | IA32OpProp_DoubleFP),