Migrate vgnop to the common codegen

We also rename `vgdnop` to `vgnop` to stay consistent across codegens.

compiler/aarch64/codegen/ARM64Debug.cpp

@@ -752,8 +752,6 @@ static const char *opCodeToNameMap[] =
    "vfneg2d",
    "vnot16b",
    "nop",
-   "return",
-   "vgdnop",
    };
 
 const char *

compiler/aarch64/codegen/ARM64Instruction.hpp

@@ -4038,7 +4038,7 @@ class ARM64VirtualGuardNOPInstruction : public TR::ARM64LabelInstruction
                                  TR::RegisterDependencyConditions *cond,
                                  TR::LabelSymbol                  *sym,
                                  TR::CodeGenerator                *cg)
-      : TR::ARM64LabelInstruction(TR::InstOpCode::vgdnop, node, sym, cond, cg),
+      : TR::ARM64LabelInstruction(TR::InstOpCode::vgnop, node, sym, cond, cg),
         _site(site)
       {
       }
@@ -4049,7 +4049,7 @@ class ARM64VirtualGuardNOPInstruction : public TR::ARM64LabelInstruction
                                  TR::LabelSymbol                  *sym,
                                  TR::Instruction                  *precedingInstruction,
                                  TR::CodeGenerator                *cg)
-      : TR::ARM64LabelInstruction(TR::InstOpCode::vgdnop, node, sym, cond, precedingInstruction, cg),
+      : TR::ARM64LabelInstruction(TR::InstOpCode::vgnop, node, sym, cond, precedingInstruction, cg),
         _site(site)
       {
       }

compiler/aarch64/codegen/OMRInstOpCode.enum

@@ -733,6 +733,5 @@
 /* Hint instructions */
 		nop,                                                    	/* 0xD503201F   NOP          */
 /* Internal OpCodes */
-		vgdnop, // Virtual Guard NOP instruction
-		ARM64LastOp = vgdnop,
+		ARM64LastOp = nop,
 		ARM64NumOpCodes = ARM64LastOp+1,

compiler/codegen/OMRCodeGenerator.cpp

@@ -2514,36 +2514,36 @@ bool OMR::CodeGenerator::areMergeableGuards(TR::Instruction *earlierGuard, TR::I
           && (!earlierGuard->getNode()->isStopTheWorldGuard() || laterGuard->getNode()->isStopTheWorldGuard());
    }
 
-TR::Instruction *OMR::CodeGenerator::getVirtualGuardForPatching(TR::Instruction *vgdnop)
+TR::Instruction *OMR::CodeGenerator::getVirtualGuardForPatching(TR::Instruction *vgnop)
    {
-   TR_ASSERT(vgdnop->isVirtualGuardNOPInstruction(),
-      "getGuardForPatching called with non VirtualGuardNOPInstruction [%p] - this only works for guards!", vgdnop);
+   TR_ASSERT(vgnop->isVirtualGuardNOPInstruction(),
+      "getGuardForPatching called with non VirtualGuardNOPInstruction [%p] - this only works for guards!", vgnop);
 
-   if (!vgdnop->isMergeableGuard())
-      return vgdnop;
+   if (!vgnop->isMergeableGuard())
+      return vgnop;
 
    // If there are no previous instructions the instruction must be the patch point
    // as there is nothing to merge with
-   if (!vgdnop->getPrev())
-      return vgdnop;
+   if (!vgnop->getPrev())
+      return vgnop;
 
    // Guard merging is only done when the guard trees are consecutive in treetop order
    // only separated by BBStart and BBEnd trees Skip back to the BBStart since we need
-   // to get the block for vgdnop
-   if (vgdnop->getPrev()->getNode()->getOpCodeValue() != TR::BBStart)
-      return vgdnop;
+   // to get the block for vgnop
+   if (vgnop->getPrev()->getNode()->getOpCodeValue() != TR::BBStart)
+      return vgnop;
 
    // there could be local RA generated reg-reg movs between guards so we resort to checking the
    // trees and making sure that the guards are in treetop order
    // we only merge blocks in the same extended blocks - virtual guard head merger will
    // arrange for this to happen when possible for guards
-   TR::Instruction *toReturn = vgdnop;
-   TR::Block *extendedBlockStart = vgdnop->getPrev()->getNode()->getBlock()->startOfExtendedBlock();
-   for (TR::Instruction *prevI = vgdnop->getPrev(); prevI; prevI = prevI->getPrev())
+   TR::Instruction *toReturn = vgnop;
+   TR::Block *extendedBlockStart = vgnop->getPrev()->getNode()->getBlock()->startOfExtendedBlock();
+   for (TR::Instruction *prevI = vgnop->getPrev(); prevI; prevI = prevI->getPrev())
       {
       if (prevI->isVirtualGuardNOPInstruction())
          {
-         if (self()->areMergeableGuards(prevI, vgdnop))
+         if (self()->areMergeableGuards(prevI, vgnop))
             {
             toReturn = prevI;
             }
@@ -2555,7 +2555,7 @@ TR::Instruction *OMR::CodeGenerator::getVirtualGuardForPatching(TR::Instruction
       else
          {
          if (prevI->isMergeableGuard() &&
-             prevI->getNode()->getBranchDestination() == vgdnop->getNode()->getBranchDestination())
+             prevI->getNode()->getBranchDestination() == vgnop->getNode()->getBranchDestination())
             {
             // instruction tied to an acceptable guard so do nothing and continue
             }
@@ -2572,26 +2572,26 @@ TR::Instruction *OMR::CodeGenerator::getVirtualGuardForPatching(TR::Instruction
             }
          }
       }
-   if (toReturn != vgdnop)
+   if (toReturn != vgnop)
       {
       TR::DebugCounter::incStaticDebugCounter(self()->comp(), TR::DebugCounter::debugCounterName(self()->comp(), "guardMerge/(%s)", self()->comp()->signature()));
       if (self()->comp()->getOption(TR_TraceCG))
-         traceMsg(self()->comp(), "vgdnop instruction [%p] begins scanning for patch instructions for mergeable guard [%p]\n", vgdnop, toReturn);
+         traceMsg(self()->comp(), "vgnop instruction [%p] begins scanning for patch instructions for mergeable guard [%p]\n", vgnop, toReturn);
       }
    return toReturn;
    }
 
 TR::Instruction
-*OMR::CodeGenerator::getInstructionToBePatched(TR::Instruction *vgdnop)
+*OMR::CodeGenerator::getInstructionToBePatched(TR::Instruction *vgnop)
    {
    TR::Instruction   * nextI;
    TR::Node          *firstBBEnd = NULL;
 
-   for (nextI=self()->getVirtualGuardForPatching(vgdnop)->getNext(); nextI!=NULL; nextI=nextI->getNext())
+   for (nextI=self()->getVirtualGuardForPatching(vgnop)->getNext(); nextI!=NULL; nextI=nextI->getNext())
       {
       if (nextI->isVirtualGuardNOPInstruction())
          {
-         if (!self()->areMergeableGuards(vgdnop, nextI))
+         if (!self()->areMergeableGuards(vgnop, nextI))
             return NULL;
          continue;
          }
@@ -2624,27 +2624,27 @@ TR::Instruction
 
 
 int32_t
-OMR::CodeGenerator::sizeOfInstructionToBePatched(TR::Instruction *vgdnop)
+OMR::CodeGenerator::sizeOfInstructionToBePatched(TR::Instruction *vgnop)
    {
-   TR::Instruction *instToBePatched = self()->getInstructionToBePatched(vgdnop);
+   TR::Instruction *instToBePatched = self()->getInstructionToBePatched(vgnop);
    if (instToBePatched)
       return instToBePatched->getBinaryLengthLowerBound();
    else
         return 0;
    }
 
 int32_t
-OMR::CodeGenerator::sizeOfInstructionToBePatchedHCRGuard(TR::Instruction *vgdnop)
+OMR::CodeGenerator::sizeOfInstructionToBePatchedHCRGuard(TR::Instruction *vgnop)
    {
    TR::Instruction   *nextI;
    TR::Node          *firstBBEnd = NULL;
    int32_t             accumulatedSize = 0;
 
-   for (nextI=self()->getInstructionToBePatched(vgdnop); nextI!=NULL; nextI=nextI->getNext())
+   for (nextI=self()->getInstructionToBePatched(vgnop); nextI!=NULL; nextI=nextI->getNext())
       {
       if (nextI->isVirtualGuardNOPInstruction())
          {
-         if (!self()->areMergeableGuards(vgdnop, nextI))
+         if (!self()->areMergeableGuards(vgnop, nextI))
             break;
          continue;
          }

compiler/codegen/OMRCodeGenerator.hpp

@@ -1288,14 +1288,14 @@ class OMR_EXTENSIBLE CodeGenerator
    // --------------------------------------------------------------------------
    // Code patching
    //
-   // Used to find out whether there is an appropriate instruction space as vgdnop space
-   int32_t sizeOfInstructionToBePatched(TR::Instruction *vgdnop);
-   int32_t sizeOfInstructionToBePatchedHCRGuard(TR::Instruction *vgdnop);
-   // Used to find which instruction is an appropriate instruction space as vgdnop space
-   TR::Instruction* getInstructionToBePatched(TR::Instruction *vgdnop);
+   // Used to find out whether there is an appropriate instruction space as vgnop space
+   int32_t sizeOfInstructionToBePatched(TR::Instruction *vgnop);
+   int32_t sizeOfInstructionToBePatchedHCRGuard(TR::Instruction *vgnop);
+   // Used to find which instruction is an appropriate instruction space as vgnop space
+   TR::Instruction* getInstructionToBePatched(TR::Instruction *vgnop);
    // Used to find the guard instruction where a given guard will actually patch
-   // currently can only return a value other than vgdnop for HCR guards
-   TR::Instruction* getVirtualGuardForPatching(TR::Instruction *vgdnop);
+   // currently can only return a value other than vgnop for HCR guards
+   TR::Instruction* getVirtualGuardForPatching(TR::Instruction *vgnop);
 
    void jitAddPicToPatchOnClassUnload(void *classPointer, void *addressToBePatched) {}
    void jitAdd32BitPicToPatchOnClassUnload(void *classPointer, void *addressToBePatched) {}

compiler/p/codegen/OMRInstOpCode.enum

@@ -541,7 +541,6 @@
    shdfence,         // Scheduling Fence
 // rxor,             // Rotate & XOR
    wrtbar,           // Write barrier directive
-   vgdnop,           // Virtual Guard NOP instruction
    probenop,         // Probe NOP (for RI)
    iflong,           // compare and branch long
    idiv,             // integer divide

compiler/p/codegen/OMRInstOpCodeProperties.hpp

@@ -102,6 +102,17 @@
    /* .properties  = */ PPCOpProp_None,
    },
 
+   {
+   /* .mnemonic    = */ OMR::InstOpCode::vgnop,
+   /* .name        = */ "vgnop",
+   /* .description =    "Virtual Guard NOP instruction", */
+   /* .prefix      = */ 0x00000000,
+   /* .opcode      = */ 0x00000000,
+   /* .format      = */ FORMAT_UNKNOWN,
+   /* .minimumALS  = */ OMR_PROCESSOR_PPC_UNKNOWN,
+   /* .properties  = */ PPCOpProp_None,
+   },
+
    {
    /* .mnemonic    = */ OMR::InstOpCode::add,
    /* .name        = */ "add",
@@ -6279,17 +6290,6 @@
    /* .properties  = */ PPCOpProp_None,
    },
 
-   {
-   /* .mnemonic    = */ OMR::InstOpCode::vgdnop,
-   /* .name        = */ "vgdnop",
-   /* .description =    "Virtual Guard NOP instruction", */
-   /* .prefix      = */ 0x00000000,
-   /* .opcode      = */ 0x00000000,
-   /* .format      = */ FORMAT_UNKNOWN,
-   /* .minimumALS  = */ OMR_PROCESSOR_PPC_UNKNOWN,
-   /* .properties  = */ PPCOpProp_None,
-   },
-
    {
    /* .mnemonic    = */ OMR::InstOpCode::probenop,
    /* .name        = */ "nop",

compiler/p/codegen/OMRPeephole.cpp

@@ -63,7 +63,7 @@ isEBBTerminatingBranch(TR::Instruction *instr)
       case TR::InstOpCode::blel:             // Branch and link if less than or equal
       case TR::InstOpCode::bltl:             // Branch and link if less than
       case TR::InstOpCode::bnel:             // Branch and link if not equal
-      case TR::InstOpCode::vgdnop:           // A vgdnop can be backpatched to a branch
+      case TR::InstOpCode::vgnop:            // A vgnop can be backpatched to a branch
          return true;
       default:
          return false;
@@ -498,9 +498,8 @@ OMR::Power::Peephole::tryToRemoveRedundantMoveRegister()
                return performed;
             }
          }
-      else if (current->getOpCodeValue() == TR::InstOpCode::vgdnop)
-         // a vgdnop can be backpatched to a branch, and so we must suppress
-         // any later attempt to remove the mr
+      else if (current->getOpCodeValue() == TR::InstOpCode::vgnop)
+         // a vgnop can be backpatched to a branch, and so we must suppress any later attempt to remove the mr
          all_mr_source_uses_rewritten = false;
       else
          {

compiler/p/codegen/OMRTreeEvaluator.cpp

@@ -550,7 +550,7 @@ static bool nodeIsNeeded(TR::Node *checkNode, TR::Node *node)
 TR::Register *OMR::Power::TreeEvaluator::aloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
    TR::Compilation *comp = cg->comp();
-   // NEW to check for it feeding to a single vgdnop
+   // NEW to check for it feeding to a single vgnop
    static bool disableLoadForVGDNOP = (feGetEnv("TR_DisableLoadForVGDNOP") != NULL);
    bool checkFeedingVGDNOP = !disableLoadForVGDNOP &&
       node->getOpCodeValue() == TR::aloadi &&

compiler/p/codegen/PPCInstruction.hpp

@@ -1462,15 +1462,15 @@ class PPCVirtualGuardNOPInstruction : public PPCDepLabelInstruction
                                     TR::RegisterDependencyConditions *cond,
                                     TR::LabelSymbol                  *label,
                                     TR::CodeGenerator               *codeGen)
-      : PPCDepLabelInstruction(TR::InstOpCode::vgdnop, node, label, cond, codeGen), _site(site) {}
+      : PPCDepLabelInstruction(TR::InstOpCode::vgnop, node, label, cond, codeGen), _site(site) {}
 
    PPCVirtualGuardNOPInstruction(TR::Node                        *node,
                                     TR_VirtualGuardSite     *site,
                                     TR::RegisterDependencyConditions *cond,
                                     TR::LabelSymbol                  *label,
                                     TR::Instruction                 *precedingInstruction,
                                     TR::CodeGenerator               *codeGen)
-      : PPCDepLabelInstruction(TR::InstOpCode::vgdnop, node, label, cond, precedingInstruction, codeGen), _site(site) {}
+      : PPCDepLabelInstruction(TR::InstOpCode::vgnop, node, label, cond, precedingInstruction, codeGen), _site(site) {}
 
    virtual Kind getKind() { return IsVirtualGuardNOP; }
 

compiler/z/codegen/OMRInstOpCode.enum

@@ -32,7 +32,6 @@
    DC2,                 // DC2
    DCB,                 // Debug Counter Bump
    DEPEND,              // Someplace to hang dependencies
-   VGNOP,               // ValueGuardNOP
 
    /* z900 Instructions */
 

compiler/z/codegen/OMRInstOpCodeProperties.hpp

@@ -82,7 +82,7 @@
 
    {
    /* .mnemonic    = */ OMR::InstOpCode::proc,
-   /* .name        = */ "PROC",
+   /* .name        = */ "proc",
    /* .description = */ "Entry to the method",
    /* .opcode[0]   = */ 0x00,
    /* .opcode[1]   = */ 0x00,
@@ -102,6 +102,17 @@
    /* .properties  = */ S390OpProp_None
    },
 
+   {
+   /* .mnemonic    = */ OMR::InstOpCode::vgnop,
+   /* .name        = */ "vgnop",
+   /* .description = */ "Virtual Guard NOP",
+   /* .opcode[0]   = */ 0xA7,
+   /* .opcode[1]   = */ 0x04,
+   /* .format      = */ PSEUDO,
+   /* .minimumALS  = */ OMR_PROCESSOR_S390_UNKNOWN,
+   /* .properties  = */ S390OpProp_None
+   },
+
    {
    /* .mnemonic    = */ OMR::InstOpCode::BREAK,
    /* .name        = */ "BREAK",
@@ -150,17 +161,6 @@
    /* .properties  = */ S390OpProp_None
    },
 
-   {
-   /* .mnemonic    = */ OMR::InstOpCode::VGNOP,
-   /* .name        = */ "VGNOP",
-   /* .description = */ "ValueGuardNOP",
-   /* .opcode[0]   = */ 0xA7,
-   /* .opcode[1]   = */ 0x04,
-   /* .format      = */ PSEUDO,
-   /* .minimumALS  = */ OMR_PROCESSOR_S390_UNKNOWN,
-   /* .properties  = */ S390OpProp_None
-   },
-
    {
    /* .mnemonic    = */ OMR::InstOpCode::A,
    /* .name        = */ "A",