You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Hi,
could you please tell me the correctness of the following sample inverter design and corresponding wrapper or suggest a forum where I can post similar queries?
I have tried to replace the caravel user project with a simple inverter design using only GPIO interface. Corresponding user project example is modified as below
module user_proj_example ( ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
similarly the user_project_wrapper is modified as below
`default_nettype none
module user_project_wrapper ( ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply inout vdda2, // User area 2 3.3V supply inout vssa1, // User area 1 analog ground inout vssa2, // User area 2 analog ground inout vccd1, // User area 1 1.8V supply inout vccd2, // User area 2 1.8v supply inout vssd1, // User area 1 digital ground inout vssd2, // User area 2 digital ground endif
The user project wrapper needs to have all pins declared---you cannot change the pin information on the wrapper, since it has to connect to the same set of defined pins in the caravel chip.
If you are doing this outside of the openlane flow, I suggest using the caravan chip, as it is better suited for just dropping a custom circuit into the user project area and wiring it up to the wrapper pins.
Hi,
could you please tell me the correctness of the following sample inverter design and corresponding wrapper or suggest a forum where I can post similar queries?
I have tried to replace the caravel user project with a simple inverter design using only GPIO interface. Corresponding user project example is modified as below
module user_proj_example (
ifdef USE_POWER_PINSinout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
);
endmodule
module inverter (
input inv_in,
output inv_out
);
wire [31:0] inv_in;
wire [31:0] inv_out;
always @(inv_in)
begin
inv_out=~inv_in;
end
endmodule
`default_nettype wire
similarly the user_project_wrapper is modified as below
`default_nettype none
module user_project_wrapper (
ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply inout vdda2, // User area 2 3.3V supply inout vssa1, // User area 1 analog ground inout vssa2, // User area 2 analog ground inout vccd1, // User area 1 1.8V supply inout vccd2, // User area 2 1.8v supply inout vssd1, // User area 1 digital ground inout vssd2, // User area 2 digital ground
endif);
user_proj_example mprj (
ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power .vssd1(vssd1), // User area 1 digital ground
endif);
endmodule // user_project_wrapper
`default_nettype wire
The text was updated successfully, but these errors were encountered: