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Sample design integration into caravel #72

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GitDiscipline opened this issue Feb 14, 2022 · 1 comment
Closed

Sample design integration into caravel #72

GitDiscipline opened this issue Feb 14, 2022 · 1 comment
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help wanted Extra attention is needed

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@GitDiscipline
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GitDiscipline commented Feb 14, 2022

Hi,
could you please tell me the correctness of the following sample inverter design and corresponding wrapper or suggest a forum where I can post similar queries?

I have tried to replace the caravel user project with a simple inverter design using only GPIO interface. Corresponding user project example is modified as below

module user_proj_example ( ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif

// IOs
input  [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,

);

wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;

wire [31:0] inv_in; 
wire [31:0] inv_out;






// IO
assign inv_in = io_in;
assign io_out = inv_out;




inverter(
    .inv_in(inv_in),
    .inv_out(inv_out),
    
);

endmodule

module inverter (
input inv_in,
output inv_out

);

wire [31:0] inv_in;
wire [31:0] inv_out;

always @(inv_in)
begin

inv_out=~inv_in;

end

endmodule
`default_nettype wire

similarly the user_project_wrapper is modified as below

`default_nettype none

module user_project_wrapper (
ifdef USE_POWER_PINS inout vdda1, // User area 1 3.3V supply inout vdda2, // User area 2 3.3V supply inout vssa1, // User area 1 analog ground inout vssa2, // User area 2 analog ground inout vccd1, // User area 1 1.8V supply inout vccd2, // User area 2 1.8v supply inout vssd1, // User area 1 digital ground inout vssd2, // User area 2 digital ground endif

// IOs
input  [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,

);

user_proj_example mprj (
ifdef USE_POWER_PINS .vccd1(vccd1), // User area 1 1.8V power .vssd1(vssd1), // User area 1 digital ground endif

// IO Pads

.io_in (io_in),
.io_out(io_out)

);

endmodule // user_project_wrapper

`default_nettype wire

@RTimothyEdwards
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The user project wrapper needs to have all pins declared---you cannot change the pin information on the wrapper, since it has to connect to the same set of defined pins in the caravel chip.

If you are doing this outside of the openlane flow, I suggest using the caravan chip, as it is better suited for just dropping a custom circuit into the user project area and wiring it up to the wrapper pins.

@SaraEfabless SaraEfabless added the help wanted Extra attention is needed label Nov 4, 2022
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