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Table of contents
- Getting Started - Directory Setup
- Getting Started - OpenLANE Flow Setup
- Getting Started - PDK Setup
- Getting Started - How to Run
- The Flow
- Regression And Design Configurations Exploration
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII - this capability will be released in the coming weeks with completed SoC design examples that have been sent to SkyWater for fabricaiton.
- Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice
- Magic VLSI Layout Tool is needed to run open_pdks -- version >= 8.3.25
For more details about the docker container and its process, the following instructions walk you through the process of using docker containers to build the needed tools then integrate them into OpenLANE flow.
Setting up the PDK: skywater-pdk
Clone and build one skywwater-pdk variant(s) inside the pdks directory:
- To setup one variant only
export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside> cd $PDK_ROOT git clone email@example.com:google/skywater-pdk.git cd skywater-pdk git checkout 4e5e318e0cc578090e1ae7d6f2cb1ec99f363120 git submodule update --init libraries/sky130_fd_sc_hd/latest make sky130_fd_sc_hd
- To setup other variants:
- replace sky130_fd_sc_hd with any of the following list:
- replace sky130_fd_sc_hd with any of the following list:
Setup the configurations and tech files for Magic, Netgen, OpenLANE using open_pdks:
cd $PDK_ROOT git clone firstname.lastname@example.org:efabless/open_pdks.git -b rc2 cd open_pdks make make install-local
To set the PDK_VARIANT (the default value is set to sky130_fd_sc_hd)
set PDK_VARIANT to one of the following:
- sky130_fd_sc_hs - sky130_fd_sc_ms - sky130_fd_sc_ls - sky130_fd_sc_hdll
Refer to this for more details on the structure.
Setting up OpenLANE
git clone email@example.com:efabless/openlane --branch rc2 cd openlane/docker_build make merge cd ..
Issue the following command to open the docker container from path/to/openlane to ensure that the output files persist after exiting the container:
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) openlane:rc2
Note: this will mount the openlane directory inside the container.
Use the following example to check the overall setup:
./flow.tcl -design spm
To run OpenLANE on multiple designs at the same time, check this section.
Command line arguments
The following are arguments that can be passed to
Specifies the design folder. A design folder should contain a config.tcl definig the design parameters.
If the folder is not found, ./designs directory is searched
Specifies the design's configuration file for while running the flow.
For example, to run the flow using
Can Specify the configuration file name in case of using
||A flag to save a runs results like .mag and .lef in the design's folder|
Specifies a different path to save the design's result. This options is to be used with the
Creates a tcl configuration file for a design.
|Flag to overwirte an existing run with the same tag|
|Flag to run openlane flow in interactive mode|
|Passes a script of interactive commands in interactive mode|
Adding a design
To add a new design, follow the instructions provided here
This file also includes useful information about the design configuration files. It also includes useful utilities for exploring and updating design configurations for each (PDK,PDK_VARIANT) pair.
OpenLANE Design Stages
OpenLANE flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLANE can also be run interactively which will be shown below.
yosys- Performs RTL synthesis
abc- Performs technology mapping
OpenSTA- Pefroms static timing analysis on the resulting netlist to generate timing reports
- Floorplan and PDN
init_fp- Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
ioplacer- Places the macro input and output ports
pdn- Generates the power distribution network
tapcell- Inserts welltap and decap cells in the floorplan
RePLace- Performs global placement
Resizer- Performs optional optimizations on the design
OpenDP- Perfroms detailed placement to legalize the globally placed components
TritonCTS- Synthesizes the clock distribution network (the clock tree)
- Routing *
FastRoute- Performs global routing to generate a guide file for the detailed router
TritonRoute- Performs detailed routing
- GDSII Generation
Magic- Streams out the final GDSII layout file from the routed def
Magic- Performs DRC Checks & Antenna Checks
Netgen- Performs LVS Checks
OpenLANE integrated several key open source tools over the execution stages:
- RTL Synthesis, Technology Mapping, and Formal Verification : yosys + abc
- Static Timing Analysis: OpenSTA
- Floor Planning: init_fp, ioPlacer, pdn and tapcell
- Placement: RePLace (Global), Resizer (Optimizations), and OpenDP (Detailed)
- Clock Tree Synthesis: OpenROAD/TritonCTS
- Fill Insertion: OpenROAD/filler_placement
- Routing: FastRoute (Global) and TritonRoute (Detailed)
- GDSII Streaming out: Magic
- DRC Checks: Magic
- LVS check: Netgen
- Antenna Checks: Magic
All output run data is placed by default under ./designs/design_name/runs. Each flow cycle will output timestamp-marked foler containing the following file structure:
designs/<design_name> ├── config.tcl ├── runs │ ├── <tag> │ │ ├── config.tcl │ │ ├── logs │ │ │ ├── cts │ │ │ ├── floorplan │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ ├── reports │ │ │ ├── cts │ │ │ ├── floorplan │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ ├── results │ │ │ ├── cts │ │ │ ├── floorplan │ │ │ ├── magic │ │ │ ├── placement │ │ │ ├── routing │ │ │ └── synthesis │ │ └── tmp │ │ ├── cts │ │ ├── floorplan │ │ ├── magic │ │ ├── placement │ │ ├── routing │ │ └── synthesis
- PDK / technology specific
- Flow specific
- Design specific
A PDK should define at least one variant for the PDK. A common configuration file for all PDK variants is located in:
Sometimes the PDK comes with several Standard Cell Libraries or Metal Stacks. Each is considered as a PDK variant. A variant configuration file defines extra variables specific to the variant. It may also override variables in the common PDK configuration file which is located in:
More on configuring a new PDK in this section
Flow specific variables are related to the flow and are initialized with default values in:
Finally, each design should have it's own configuration file with some required variables which are available in this list. A design configuration file may override any of the variables defined in PDK or flow configuration files. This is the global configurations for the design:
- More on design configurations in here
A list of all available variables can be found here.
You may run the flow interactively by using the
A tcl shell will be opened where the openlane package is automatically sourced:
% package require openlane 0.9
Then, you should be able to run the following commands:
- Any tcl command.
prep -design <design> -tag <tag> -config <config> -init_design_config -overwritesimilar to the command line arguments, design is required and the rest is optional
The above commands can also be written in a file and passed to
./flow.tcl -interactive -file <file>
Note 1: Currently, configuration variables have higher priority over the above commands so if
RUN_MAGIC is 0, command
run_magic will have no effect.
Note 2: Currently, all these commands must be run in sequence and none should be omitted.
Regression And Design Configurations Exploration
As mentioned earlier, everytime a new design or a new (PDK,PDK_VARIANT) pair is added, or any update happens in the flow tools, a re-configuration for the designs is needed. The reconfiguration is methodical and so an exploration script was developed to aid the designer in reconfiguring his designs if needed. As explained here that each design has multiple configuration files for each (PDK,PDK_VARIANT) pair.
run_designs.py, a script that can do multiple runs in a parallel using different configurations. A run consists of a set of designs and a configuration file that contains the configuration values. It is useful to explore the design implementation using different configurations to figure out the best one(s).
Also, it can be used for testing the flow by running the flow against several designs using their best configurations. For example the following run: spm using its default configuration files
python3 run_designs.py --designs spm xtea md5 aes256 --tag test --threads 3
For more information on how to run this script, refer to this file
For more information on design configurations, how to update them, and the need for an exploration for each design, refer to this file