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Flow and step for opening designs in Magic (#463)
## Steps * New step, `Magic.OpenGUI`, which opens either DEF files or GDS files in magic * `Magic.*` * Fixed `magicrc` being `abspath`'d before command invocation (breaks reproducibles) * `_MAGIC_SCRIPT` is now set in `prepare_env` instead of `run_subprocess` (so it can be intercepted for reproducibles) * `KLayout.OpenGUI` * Renamed `KLAYOUT_PRIORITIZE_GDS` to `KLAYOUT_GUI_USE_GDS` to be consistent with the Magic steps ## Flows * New mono-step flow, `OpenInMagic`, which runs `Magic.OpenGUI` ## Tool Updates * OpenLane 2 now uses `nix-eda` for some of its derivations * Magic now uses tk with X11 on macOS, to prevent crashes when attempting to use the GUI * Updated Magic to `8.3.483`/`291ba96` ## Misc Bugfixes/Enhancements * `openlane.steps.Step.create_reproducible` * `PDK_ROOT` now included if the PDK is included but not flattened so Magic steps can work * `openlane.steps.TclStep` * **Internal**: Internal environment variables prefixed with `_` are no longer rerouted to `_env.tcl`, instead being passed raw (to help with creating reproducibles)
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libparse | ||
psutil | ||
klayout-pymod | ||
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# Ruby | ||
ruby | ||
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# Resolving LVS Mismatches in OpenLane | ||
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This guide aims to document a number of common {term}`LVS` mismatches, their | ||
possible causes, and how to resolve them. | ||
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This is a living document. We'll add more sections as we encounter more LVS | ||
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## About LVS Mismatches | ||
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LVS mismatches (alternately referred to simply as LVS errors) constitute a | ||
situation where the physical **layout** of the chip does not match the declared | ||
**schematic** thereof. Here is a non-exhaustive list of some common issues that | ||
are captured by LVS: | ||
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1. An open circuit exists in the layout where it should be connected in the | ||
schematic, i.e., a connection was not properly made. | ||
1. A bridge exists between two wires in the layout that are not connected in | ||
the schematic, creating a short-circuit. | ||
1. A component (standard cell or macro) declared in the schematic is missing | ||
or different in the layout. | ||
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The first two are the most common class of LVS error. In OpenLane, the affected | ||
nets are more often than not power nets. | ||
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These mismatches can occur either by user misconfiguration | ||
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## Identifying LVS mismatches | ||
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When running the {flow}`Classic` flow, you may see this message at the end of | ||
the flow: | ||
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```log | ||
ERROR The following error was encountered while running the flow: | ||
One or more deferred errors were encountered: | ||
1 LVS errors found. | ||
``` | ||
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This indicates that both: | ||
* The {step}`Netgen.LVS` was run, comparing the final Verilog netlist with the | ||
final {term}`SPICE` netlist, found one mismatch. | ||
* Another step, {step}`Checker.LVS`, reported it to the flow as an Error. | ||
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We can find the specific LVS mismatches in the reports directory of | ||
{step}`Netgen.LVS`, which would be named something along the lines | ||
`runs/<run_tag>/<step number>-netgen-lvs/reports`. Inside, there is a report | ||
named `lvs.netgen.rpt`. | ||
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You can find specific mismatches by searching `MISMATCH` in the report. | ||
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## Pin postfixed with `_uqX` | ||
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In some instance, the layout may contain a pin postfixed with `_uq` and then | ||
an integer. | ||
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This typically indicates that there's a break in the net. During SPICE netlist | ||
extraction with Magic, Magic ensures every net has a unique name, meaning that | ||
if two nets exist with the same name (i.e. the same net has a break in it,) | ||
one will be renamed to `_uq`. This may be any number of things, including: | ||
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