wrong ADC Base Address of STM32L0

[shufps]

Hi,

I've been fighting with the ADC for the L0 for almost an entire weekend now ...

I managed to create a new ADC variant l0 that compiles fine to the PAC supporting the extra registers of the device but I struggled a lot to get the ADC going.

Now I figured out that the base address of the ADC is wrong but I couldn't find out from where it actually comes from.

Does someone heave an idea?

pretty pleeeaaasy 🥺

edit: Uhm, hmm ... This is from the stm32l052 header file:

#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
#define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)

ADC1_BASE is the correct address and ADC_BASE is the wrong. Why does it have two BASE addresses that are different? 😵‍💫

edit2: I think I found it ... 🤦‍♂️

let addr = if (chip_name.starts_with("STM32F0") || chip_name.starts_with("STM32L1")) && pname == "ADC" {
    defines.get_peri_addr("ADC1")
}

PS: probably I will add the new registers to the v1 and do some #[cfg(stm32_l0)] cases in the v1.rs code because it actually shouldn't be a lot different. But first things first 😬

[shufps]

is fixed: #381