Test of the USB3 IP Core from Daisho on a Xilinx device
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README.md

Test of the USB3 IP Core from Daisho on a Xilinx device

In this repository we are testing the USB3 IP Core from Daisho on a Xilinx device.

  • USB2 / ULPI working :) (vendor agnostic)
  • USB3 / PIPE working :) (IDDR/ODDR and PLL specific to Xilinx)

This work was supported by TimVideos.us and with a generous loan of a USB3.0 protocol analyzer from the Daisho project.

The design currently uses a TUSB1310A for interfacing with the USB3.0 connector. Future plans include replacing this part using the high speed transceivers (GTPs/GTXs) found in Artix-7/Kintex-7 FPGAs.

The current work is being done with;

The FMC module has 3 x USB3.0 ports. Two are connected via TUSB1310A ICs and the third is connected directly to the high speed transceivers.

[1]: As HA/HB pins from HPC FMC are not connected on Xilinx on devboards, second TUSB1310A is not usable with the KC705.

[2]: As the Nexys Video has only a LPC FMC connector, only a limited amount set of the functionality is avalible, but it is enough to prove the design also works on the Artix-7 FPGA.