cpu/rocket: increase IRQ lines to 8

enjoy-digital · Jan 14, 2022 · c3b94a3 · c3b94a3
1 parent cdacba0
commit c3b94a3
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Showing 2 changed files with 5 additions and 5 deletions.
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
@@ -125,7 +125,7 @@ def __init__(self, platform, variant="standard"):
         self.variant   = variant
 
         self.reset     = Signal()
-        self.interrupt = Signal(4)
+        self.interrupt = Signal(8)
 
         mem_dw, mmio_dw, num_cores = CPU_SIZE_PARAMS[self.variant]
 

diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c
@@ -35,11 +35,11 @@ void plic_init(void)
 {
 	int i;
 
-	// priorities for interrupt pins 1..4
-	for (i = 1; i <= 4; i++)
+	// priorities for interrupt pins 1..8
+	for (i = 1; i <= 8; i++)
 		*((unsigned int *)PLIC_BASE + i) = 1;
-	// enable interrupt pins 1..4
-	*((unsigned int *)PLIC_ENABLED) = 0xf << 1;
+	// enable interrupt pins 1..8
+	*((unsigned int *)PLIC_ENABLED) = 0xff << 1;
 	// set priority threshold to 0 (any priority > 0 triggers interrupt)
 	*((unsigned int *)PLIC_THRSHLD) = 0;
 }