v0.11.0-esp32-20220411
·
1523 commits
to master
since this release
2022/04/11 Release, based on OpenOCD v0.11.0
Features:
- Synchronized with upstream.
- esp/ci: Added build for MacOS ARM64.
- esp-config: Added Espressif USB bridge board configs.
- esp/flash: Added octal flash support.
- esp/flash: Added MXIC 32MB flash chip support. Solves problem mention in #218.
- esp/freertos: Print FreeRTOS kernel version.
- esp/freertos: Read TCB_t offsets from ESP-IDF symbol table. This adds support for different TCB block layouts which can be caused by different FreeRTOS configurations.
- esp/semihosting: Refactored code and minimized arch-specific changes in common semihosting implementation.
- semihosting: Added 'arm semihosting_basedir' command. See description here
Bug fixes:
- xtensa: Call 'keep_alive during' register/memory restore to avoid gdb warning.
- esp32s3: Added automatic target reset upon GDB connection if memory protection is enabled (#190, #183, #176 (comment))
- esp/xtensa: Added support for proper Xtensa semihosting break instruction. According to Xtensa spec 'break 1,14' should be used for semihosting calls. This will be fixed in IDF soon too.
- target/esp: Fixed ESP32-S2 & S3 IROM region boundaries. It could lead to ROM debugging problems.
- esp_riscv: Fix SBA access alignment for size < sba_access_size.