fix: Reading external register with 0 latency

[Xtyll]

Problems:

• In case of 0 latency response of the external registers user have incorrect data with AXILite and Avalon bus
• In case of APB bus and 0 latency bridge local bus <> APB was broken

What's new:

• Added tests with 0 latency to the bridges TB
• Added tests with 0 latency to regmap TB

What's fixed:

• APB bus in case of 0 latency read response
• regmap in case of 0 latency read response from external response (FWFT FIFO)

Note:
Added one additional clock delay to data reading just to implement the same code for zero and non-zero latency cases

[stridge-cruxml]

Hi @Xtyll,

You are correct, thanks for the fix!

I have verified that this fixes the issue with the verilog version (i didn't test the others).

Sorry for the slow reply too.

[arnfol]

Looks good to me, I've also checked vhdl generation with my testbench.