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Repeated definition for output clock divide by 64 in function select_r_div #89

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hwstar opened this issue Jul 20, 2022 · 0 comments
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@hwstar
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hwstar commented Jul 20, 2022

In the function select_r_div, I have a question about lines 1731 through 1740. The else-if blocks are are exactly the same and are redundant. See this snippet below. Is this intentional or is it a mistake?

uint8_t Si5351::select_r_div(uint64_t *freq)
{
.
.
.
#Line 1731
else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 2) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 4))
{
r_div = SI5351_OUTPUT_CLK_DIV_64;
*freq *= 64ULL;
}
else if((*freq >= SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 2) && (*freq < SI5351_CLKOUT_MIN_FREQ * SI5351_FREQ_MULT * 4))
{
r_div = SI5351_OUTPUT_CLK_DIV_64;
*freq *= 64ULL;
}
.
.
.
}

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