ferdirizaldi / CPU-Simulation-Verilog Public

Notifications You must be signed in to change notification settings
Fork 0
Star 0

Basic CPU design with verilog. and observed with simulated machine gtkwave

0 stars 0 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU.v		ALU.v
CPU1.v		CPU1.v
CPU1.vcd		CPU1.vcd
CPU1_tp.v		CPU1_tp.v
CPU1b.gtkw		CPU1b.gtkw
README.md		README.md
a.out		a.out
decoder.v		decoder.v
define.v		define.v
regfile.v		regfile.v

Repository files navigation

CPU-Simulation-Verilog

Basic CPU design with verilog. and observed with simulated machine gtkwave

About

Basic CPU design with verilog. and observed with simulated machine gtkwave

design cpu verilog gtkwave

Report repository

Releases

No releases published

Packages

No packages published

Languages

Verilog 100.0%