Support A Resource-Minimizing strategy ("AREA") for AWS-FPGA

[davidbiancolin]

This can materialize >10% LUT saving on some designs over the default TIMING. It uses the "AreaOptimized_high" synthesis directive, which UG901 describes as:

Performs general area optimizations including forcing ternary adder implementation, applying new thresholds for use of carry chain in comparators, and implementing area-optimized multiplexers.

I have not done any serious design space exploration of the strategy, but i have little reason to believe this won't be beneficial in most resource-constrained cases. FWIW, I also tried the LogicCompaction directive, which does help, but not as much AreaOptimized_high which inferred new BRAMs (LogicCompaction did not), likely in addition to preforming many of the same optimizations.

Related PRs / Issues

firesim/aws-fpga-firesim#54

UI / API Impact

Adds a new class "Area" that can be specified through the PLATFORM config.

Verilog / AGFI Compatibility

N/C

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[abejgonzalez]

LGTM