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bitgen error #64

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zjb2023 opened this issue May 28, 2024 · 1 comment
Open

bitgen error #64

zjb2023 opened this issue May 28, 2024 · 1 comment
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help wanted Extra attention is needed

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@zjb2023
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zjb2023 commented May 28, 2024

user_logic_error

bitgen_error

the vFPGA_top.sv
intsanted some modules can't be find can anyone help to find

rdma_base_slv inst_rdma_base_slv (
.aclk(aclk),
.aresetn(aresetn),

.axi_ctrl(axi_ctrl),

.mux_ctid(mux_ctid)

);

mux_host_card_rd_rdma inst_mux_send (
.aclk(aclk),
.aresetn(aresetn),

.mux_ctid(mux_ctid),
.s_rq(rq_rd),
.m_sq(sq_rd),

.s_axis_host(axis_host_recv[0]),
.s_axis_card(axis_card_recv[0]),
.m_axis(/*axis_rdma_send[0]*/)//

);

mux_host_card_wr_rdma inst_mux_recv (
.aclk(aclk),
.aresetn(aresetn),

.mux_ctid(mux_ctid),
.s_rq(rq_wr),
.m_sq(sq_wr),

.s_axis(/*axis_rdma_recv[0]*/),//
.m_axis_host(axis_host_send[0]),
.m_axis_card(axis_card_send[0])

);

@JonasDann
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On our end building Coyote with RDMA works. Please give a detailed explanation what exactly you are trying to do. Otherwise, we can't help you.

@bo3z bo3z added the help wanted Extra attention is needed label Oct 22, 2024
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