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Unable to poke value to dynamically generated MixedVec Bundle #1031
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For you guys convenience, such error can be reproduced by code simplified as below
The way to use MixedVec is actually follow the way introduced in Chisel Documatation here :
Exception Stack is the same
|
May be related to #1027 |
I have the same error with Chisel 3.1.8. I declared a MixedVec in my interface: class WbInterconOneMaster(val awbm: WbMaster,
val awbs: Seq[WbSlave]) extends Module {
val io = IO(new Bundle{
val wbm = Flipped(new WbMaster(awbm.dwidth, awbm.awidth))
val wbs = MixedVec(awbs.map{i => Flipped(new WbSlave(i.dwidth, i.awidth, i.iname))})
}) And tryied to poke value in my testbench : for(wbs <- dut.io.wbs) {
poke(wbs.ack_o, 0)
} But got this error at execution time (verilator backend): [info] java.util.NoSuchElementException: head of empty list
[info] at scala.collection.immutable.Nil$.head(List.scala:420)
[info] at scala.collection.immutable.Nil$.head(List.scala:417)
[info] at scala.collection.mutable.Stack.top(Stack.scala:132)
[info] at chisel3.internal.naming.NamingStack.pop_return_context(Namer.scala:133)
[info] at chisel3.util.MixedVec.length(MixedVec.scala:81)
[info] at scala.collection.IndexedSeqLike$class.iterator(IndexedSeqLike.scala:90)
[info] at chisel3.util.MixedVec.iterator(MixedVec.scala:81)
[info] at scala.collection.IterableLike$class.foreach(IterableLike.scala:72)
[info] at chisel3.util.MixedVec.foreach(MixedVec.scala:81)
[info] at wbplumbing.TestWbInterconDualSlave.<init>(testwbplumbing.scala:61) |
Does it work with master? |
I don't tested with master. If I want to test master, do I just have to change Chisel version with snapshot in build.sbt? |
@edwardcwang Did you do some PR that addresses this. I have an example that fails as described here but works properly when I use current chisel master. Would be nice to reference the fix, whatever it is then close this. |
Hi, I'm using MixedVec to dynamically generate Bundle based on String as shown below (real case is a little bit more complicated but the error is the same).
You can simply run BugMain below to reproduce such error.
Reproduce Step:
1. create a array of String in "BugMain", io of module "bug_hw" is instantiate based on that array.
2. method "get_io" take string array and generate different io types in MixedVec.
3. Verilog file can be generated successfully.
4. In "BugUnitTester", io is actually "java.util.NoSuchElementException" (supposed to be MixedVec[Data])
Type of issue: bug report
Impact: unknown
HOW TO REPRODUCE:
Code:
What is the current behavior?
Error Stack
What is the expected behavior?
I should be able to refer io of module in BugUnitTester to poke value
Please tell us about your environment:
sbt version = 1.1.2
scala version = 2.11.12
chisel version = 3.1.6
chisel iotester version = 1.2.8
firrtl interpreter version = 1.1.6
OS: Ubuntu 16.04 LTS
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