unnecessary dual-port RAM

[pentin-as]

When I write this code:
val mem = SeqMem (...)
when (a || b) {
mem.write (...)
}
mem.read (...,!a &&!b && ...)
I have a dual-port RAM.

When I write this code:
val mem = SeqMem (...)
val need_write = a || b
when (need_write) {
mem.write (...)
}
mem.read (...,!need_write && ...)
I have a single-port RAM.

As far as I understand, when there is combinatorial logic in "when", an intermediate signal is created in fir-code, which does not exist in "read".

I propose to make either chisel or firrtl more clever in this part.

[aswaterman]

You should write the code in the more stylized manner of your second example. While it's straightforward to pattern-match your first example, the more general problem requires a logic optimizer to prove mutual exclusivity. That would be nice to have, but it's a lot of work. We don't plan to pattern-match specific cases (like your first example) because it's an incomplete solution to the problem, and we will instead hold out for a more robust analysis.