Awesome HDL

A curated list of awesome HDL, libraries and implementation (by language). Inspired by awesome-machine-learning.

If you want to contribute to this list (please do), please feel free to send me a pull request .

Table of Contents

• Verilog-Toolkit
• Verilog-Implementation
• Verilog-Books
• VHDL-Toolkit
• VHDL-Implementation
• Tutorial
• Paper

## Verilog-Toolkit * [Icarus Verilog](https://github.com/steveicarus/iverilog) - A Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.

• verilog-mode - Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs.

• Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL.

• veriloggen - A library for constructing a Verilog HDL source code by Python.

• PyCoRAM - Python-based Portable IP-core Synthesis Framework for FPGA-based Computing.

• Pyverilog-toolbox - Pyverilog-based verification/design tool including code clone finder, metrics calculator and so on.

## Hardware-Implementation-by-Verilog * [miaow](https://github.com/VerticalResearchGroup/miaow) - An open source GPU based off of the AMD Southern Islands ISA.

• amiga2000-gfxcard - MNT VA2000, an Amiga 2000 Graphics Card (Zorro II), written in Verilog.

• gplgpu - GPL v3 2D/3D graphics engine in verilog.

• oh - Silicon validated Open Verilog library for IC and FPGA designers.

• FPGA-Litecoin-Miner - Litecoin script miner implemented with FPGA on-chip memory.

• verilog-ethernet - Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths).

## Verilog-Books * [SystemVerilog Assertions Handbook](https://verificationacademy.com/forums/systemverilog/new-book-systemverilog-assertions-handbook-4th-edition) - Assertion Guide for static and dynamic verification.

• Writing Testbenches using SystemVerilog - Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source.

## VHDL-Toolkit * [sublime-vhdl](https://github.com/yangsu/sublime-vhdl) - VHDL Package for Sublime Text 2/3.

• nvc - VHDL compiler and simulator.

• vunit - A unit testing framework for VHDL/SystemVerilog.

## Hardware-Implementation-by-VHDL * [Open-Source-FPGA-Bitcoin-Miner](https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner) - A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs.

• space-invaders-vhdl - Space Invaders game implemented with VHDL.

## Tutorial

• IntroToSpartanFPGABook - A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards.

• EDA playground - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

## Paper

• Asynchronous & Synchronous Reset Design Techniques

• Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog