Added syntax highlighting keywords for Verilog-2001 "generate" statement and localparams. Added syntax highlighting for BSDL files as VHDL.

data/filedefs/filetypes.verilog

@@ -23,9 +23,9 @@ port_connect=keyword_4
 
 [keywords]
 # all items must be in one line
-word=always and assign attribute begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endattribute endcase endfunction endmodule endprimitive endspecify endtable endtask event for force forever fork function highz0 highz1 if ifnone initial join medium module large macromodule nand negedge nmos nor not notif0 notif1 or parameter pmos posedge primitive pull0 pull1 pulldown pullup rcmos realtime release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared signed small specify specparam strength strong0 strong1 supply0 supply1 table task tran tranif0 tranif1 tri tri0 tri1 triand trior trireg unsigned vectored wait wand weak0 weak1 while wor xnor xor @
-word2=$display $write $fdisplay $fwrite $strobe $fstrobe $monitor $fmonitor $time $realtime $finish $stop $setup $hold $width $setuphold $readmemb $readmemh $sreadmemb $sreadmemh $getpattern $history $save $restart $incsave $shm_open $shm_probe $shm_close $scale $showscopes $showvars
-word3=real integer time reg wire input output inout
+word=always and assign attribute begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endattribute endcase endfunction endgenerate endmodule endprimitive endspecify endtable endtask event for force forever fork function generate highz0 highz1 if ifnone initial join medium module large localparam macromodule nand negedge nmos nor not notif0 notif1 or parameter pmos posedge primitive pull0 pull1 pulldown pullup rcmos realtime release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared signed small specify specparam strength strong0 strong1 supply0 supply1 table task tran tranif0 tranif1 tri tri0 tri1 triand trior trireg unsigned vectored wait wand weak0 weak1 while wor xnor xor @
+word2=$display $fdisplay $finish $fmonitor $fstrobe $fwrite $getpattern $history $hold $incsave $monitor $realtime $readmemb $readmemh $restart $save $scale $setup $setuphold $shm_close $shm_open $shm_probe $showscopes $showvars  $sreadmemb $sreadmemh $stop $strobe $time $width $write
+word3=genvar inout input integer output real reg time wire
 docComment=
 
 [settings]

data/filetype_extensions.conf

@@ -66,7 +66,7 @@ Tcl=*.tcl;*.tk;*.wish;*.exp;
 Txt2tags=*.t2t;
 Vala=*.vala;*.vapi;
 Verilog=*.v;
-VHDL=*.vhd;*.vhdl;
+VHDL=*.vhd;*.vhdl;*.bsdl;
 XML=*.xml;*.sgml;*.xsl;*.xslt;*.xsd;*.xhtml;*.xul;*.dtd;*.xtpl;*.mml;*.mathml;
 YAML=*.yaml;*.yml;
 Zephir=*.zep;