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mem-ruby: Remove VIPER StoreThrough temp cache storage #1156

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merged 1 commit into from
May 28, 2024

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@abmerop abmerop commented May 21, 2024

StoreThrough in VIPER when the TCP is disabled, GLC bit is set, or SLC bit is set will bypass the TCP, but will temporarily allocate a cache entry seemingly to handle write coalescing with valid blocks. It does not attempt to evict a block if the set is full and the address is invalid. This causes a panic if the set is full as there is no spare cache entry to use temporarily to use for DataBlk manipulation. However, a cache block is not required for this.

This commit removes using a cache block for StoreThrough with invalid blocks as there is no existing data to coalesce with. It creates no allocate variants of the actions needed in StoreThrough and pulls the DataBlk information from the in_msg instead. Non-invalid blocks do not have this panic as they have a cache entry already.

Fixes issues with StoreThroughs on more aggressive architectures like MI300.

Change-Id: Id8687eccb991e967bb5292068cbe7686e0930d7d

@abmerop abmerop added bug gpu gem5's GPU Simulation infrastructure labels May 21, 2024
@abmerop abmerop requested a review from mattsinc May 21, 2024 22:01
StoreThrough in VIPER when the TCP is disabled, GLC bit is set, or SLC
bit is set will bypass the TCP, but will temporarily allocate a cache
entry seemingly to handle write coalescing with valid blocks. It does
not attempt to evict a block if the set is full and the address is
invalid. This causes a panic if the set is full as there is no spare
cache entry to use temporarily to use for DataBlk manipulation. However,
a cache block is not required for this.

This commit removes using a cache block for StoreThrough with invalid
blocks as there is no existing data to coalesce with. It creates no
allocate variants of the actions needed in StoreThrough and pulls the
DataBlk information from the in_msg instead. Non-invalid blocks do not
have this panic as they have a cache entry already.

Fixes issues with StoreThroughs on more aggressive architectures like
MI300.

Change-Id: Id8687eccb991e967bb5292068cbe7686e0930d7d
@abmerop abmerop added this to the v24.0 milestone May 24, 2024
@mattsinc
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@v-ramadas FYI

@abmerop abmerop merged commit e82cf20 into gem5:develop May 28, 2024
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@abmerop abmerop deleted the actually-storethrough branch June 11, 2024 18:16
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2 participants