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cmd/compile: adding a constant to a memory location needs 3 instructions #15054

brtzsnr opened this Issue Mar 31, 2016 · 5 comments


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brtzsnr commented Mar 31, 2016

Please answer these questions before submitting your issue. Thanks!

  1. What version of Go are you using (go version)?
    go version devel +e775b8d Thu Mar 31 18:41:30 2016 +0000 linux/amd64
  2. What operating system and processor architecture are you using (go env)?
    linux amd64
  3. What did you do?
    Compiled the following function
func g(a *int) {
        *a += 3
  1. What did you expect to see?
    One single instruction
ADDQ (CX), $3
  1. What did you see instead?
    Three instructions

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brtzsnr commented Mar 31, 2016

@randall77 I don't know if it's easy or not to handle this.


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minux commented Mar 31, 2016


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randall77 commented Mar 31, 2016

This should be easier than #14587, as we don't have to deal with flags. You'd just need to make sure there are no other uses of the load. Then it would just be a simple rewrite.
The challenge is just the bulk of it. You'd want all the possible addressing modes, plus all the ops (ADD, SUB, AND...). In addition, this is something that only x86 can do, all the other archs are load-store architectures which can't do this.
I'm leaning toward punting on this for now. When the SSA backend gets more mature we can revisit.


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rasky commented Apr 1, 2016

We could... generate the rules :)

@bradfitz bradfitz added the Performance label Apr 7, 2016

@bradfitz bradfitz added this to the Unplanned milestone Apr 7, 2016


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gopherbot commented Oct 17, 2016

CL mentions this issue.

gopherbot pushed a commit that referenced this issue Oct 17, 2016

cmd/compile: merge loads into operations on s390x
Adds the new canMergeLoad function which can be used by rules to
decide whether a load can be merged into an operation. The function
ensures that the merge will not reorder the load relative to memory
operations (for example, stores) in such a way that the block can no
longer be scheduled.

This new function enables transformations such as:

MOVD 0(R1), R2
ADD  R2, R3


ADD  0(R1), R3

The two-operand form of the following instructions can now read a
single memory operand:

 - ADD
 - SUB
 - AND
 - OR
 - ORW
 - XOR

Improves SHA3 performance by 6-8%.

Updates #15054.

Change-Id: Ibcb9122126cd1a26f2c01c0dfdbb42fe5e7b5b94
Run-TryBot: Michael Munday <>
TryBot-Result: Gobot Gobot <>
Reviewed-by: Keith Randall <>
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