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Merge pull request #594 from google/revert-591-litex-bump-528
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Revert "Litex bump for issue 582"
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@tcal-x
tcal-x committed May 25, 2022
2 parents 0cb4203 + 43a6913 commit 07dda52
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Showing 12 changed files with 12 additions and 12 deletions.
2 changes: 1 addition & 1 deletion third_party/python/amaranth
Submodule amaranth updated 10 files
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2 changes: 1 addition & 1 deletion third_party/python/jinja
Submodule jinja updated 31 files
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2 changes: 1 addition & 1 deletion third_party/python/litedram
Submodule litedram updated 23 files
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+5 −5 bench/arty.py
+6 −12 bench/ddr3_mr_gen.py
+5 −5 bench/genesys2.py
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2 changes: 1 addition & 1 deletion third_party/python/liteeth
Submodule liteeth updated 15 files
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+9 −62 liteeth/core/__init__.py
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2 changes: 1 addition & 1 deletion third_party/python/litehyperbus
Submodule litehyperbus updated 2 files
+92 −121 litehyperbus/core/hyperbus.py
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2 changes: 1 addition & 1 deletion third_party/python/liteiclink
Submodule liteiclink updated 11 files
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+3 −2 bench/serdes/kc705.py
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+5 −3 bench/serdes/versa_ecp5.py
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+4 −3 bench/serwb/nexys_video.py
+3 −3 bench/serwb/ulx3s.py
+236 −795 liteiclink/serdes/gth_ultrascale.py
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2 changes: 1 addition & 1 deletion third_party/python/litepcie
Submodule litepcie updated 44 files
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+0 −199 bench/acorn.py
+0 −80 bench/test_ltssm_tracer.py
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+21 −35 litepcie/gen.py
+6 −62 litepcie/phy/common.py
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+2 −2 litepcie/phy/xilinx_usp_gen2_x4/pcie_usp_support.v
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+19 −41 litepcie/software/kernel/config.h
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+2 −1 litepcie/tlp/common.py
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+21 −32 test/model/chipset.py
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2 changes: 1 addition & 1 deletion third_party/python/litespi
Submodule litespi updated 3 files
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+2 −0 litespi/core/mmap.py
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2 changes: 1 addition & 1 deletion third_party/python/litex
Submodule litex updated 145 files
2 changes: 1 addition & 1 deletion third_party/python/litex_boards
Submodule litex_boards updated 162 files
2 changes: 1 addition & 1 deletion third_party/python/migen
Submodule migen updated 1 files
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2 changes: 1 addition & 1 deletion third_party/python/pythondata_cpu_vexriscv
Submodule pythondata_cpu_vexriscv updated 33 files
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+1,516 −1,545 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
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+1 −6 pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala

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