Skip to content

Commit

Permalink
Merge pull request #591 from google/litex-bump-528
Browse files Browse the repository at this point in the history
Litex bump for issue 582
  • Loading branch information
tcal-x committed May 23, 2022
2 parents c990c3d + 6918cb5 commit d3976a9
Show file tree
Hide file tree
Showing 12 changed files with 12 additions and 12 deletions.
2 changes: 1 addition & 1 deletion third_party/python/litehyperbus
2 changes: 1 addition & 1 deletion third_party/python/litepcie
Submodule litepcie updated 44 files
+6 −2 CONTRIBUTORS
+199 −0 bench/acorn.py
+9 −5 bench/fk33.py
+3 −2 bench/kc705.py
+5 −4 bench/kcu105.py
+80 −0 bench/test_ltssm_tracer.py
+5 −4 bench/xcu1525.py
+5 −5 examples/ac701.yml
+44 −0 examples/acorn.yml
+5 −5 examples/kcu105.yml
+29 −19 litepcie/common.py
+4 −4 litepcie/core/common.py
+14 −10 litepcie/core/crossbar.py
+12 −7 litepcie/core/endpoint.py
+1 −1 litepcie/core/msi.py
+63 −54 litepcie/frontend/dma.py
+35 −21 litepcie/gen.py
+62 −6 litepcie/phy/common.py
+14 −6 litepcie/phy/s7pciephy.py
+62 −17 litepcie/phy/uspciephy.py
+62 −15 litepcie/phy/usppciephy.py
+2 −2 litepcie/phy/xilinx_usp_gen2_x4/pcie_usp_support.v
+2 −2 litepcie/phy/xilinx_usp_gen3_x16/pcie_usp_support.v
+2 −2 litepcie/phy/xilinx_usp_gen3_x4/pcie_usp_support.v
+2 −2 litepcie/phy/xilinx_usp_gen3_x8/pcie_usp_support.v
+2 −2 litepcie/phy/xilinx_usp_hbm_gen2_x4/pcie_usp_support.v
+2 −2 litepcie/phy/xilinx_usp_hbm_gen3_x4/pcie_usp_support.v
+41 −19 litepcie/software/kernel/config.h
+23 −7 litepcie/software/kernel/main.c
+1 −5 litepcie/software/user/Makefile
+0 −68 litepcie/software/user/litepcie_dma_minimal_example.c
+66 −37 litepcie/software/user/litepcie_test.c
+152 −116 litepcie/software/user/litepcie_util.c
+1 −2 litepcie/tlp/common.py
+3 −3 litepcie/tlp/controller.py
+15 −10 litepcie/tlp/depacketizer.py
+136 −31 litepcie/tlp/packetizer.py
+32 −21 test/model/chipset.py
+11 −7 test/model/host.py
+1 −1 test/model/phy.py
+29 −5 test/model/tlp.py
+21 −11 test/test_dma.py
+6 −6 test/test_examples.py
+1 −1 test/test_wishbone.py
2 changes: 1 addition & 1 deletion third_party/python/litespi
2 changes: 1 addition & 1 deletion third_party/python/litex
Submodule litex updated 145 files
2 changes: 1 addition & 1 deletion third_party/python/litex_boards
Submodule litex_boards updated 162 files
2 changes: 1 addition & 1 deletion third_party/python/migen
2 changes: 1 addition & 1 deletion third_party/python/pythondata_cpu_vexriscv
Submodule pythondata_cpu_vexriscv updated 33 files
+2 −1 .github/workflows/publish-to-pypi.yml
+14 −5 README.md
+6 −6 pythondata_cpu_vexriscv/__init__.py
+17 −7 pythondata_cpu_vexriscv/verilog/Makefile
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv.v
+38 −2 pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
+1,429 −1,435 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
+1,545 −1,516 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml
+38 −2 pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
+38 −2 pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
+38 −2 pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
+5,350 −0 pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
+5 −0 pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
+4,312 −0 pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
+1 −0 pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
+38 −2 pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v
+1 −1 pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.yaml
+1 −1 pythondata_cpu_vexriscv/verilog/ext/VexRiscv
+6 −1 pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala

0 comments on commit d3976a9

Please sign in to comment.