FPGA Main Blocks

Here the main blocks on the FPGA are explained.

FPGA Main Blocks

Index

The timestamp is used if the user wants to save a timestamp together with the data.
Each channel has it’s own timestamp counter but all of them will be clocked from the same clock on the FPGA
The channel controllers will (if it is enabled) embed the timestamp with the received data that is sent to the FIFO.
If the user enables timestamp when there is data already saved in the memory the data has to be cleared, (prompt the user!)
Timestamp on transmitted data????
The timestamp should be independently resettable for each channel
The resolution should be configurable by the user???

At the lowest abstraction level the data in the memory is just a bunch of bytes saved in sequence in each channel-block.
How these bytes are interpreted is up to the MCU connected to the FPGA to take care of.
Information about the format can be found in the Channel registers, i.e. timestamp enabled, channel type, TX/RX, etc.
This information should not have to be read every time data is transferred from FPGA to MCU but only when something changes and at startup.
The formatting means different amount of data can be saved depending on how a channel is configured. This amount should be available to the user somehow

At startup after everything has settled (how long to wait?) the ID’s will be read from the external A/D converter and stored in the ID Register of the ID Reader Controller
After this all the channel can read the ID Register and configure it self to the specified channel type
If the ID is invalid the ID Reader Controller should retry (how many times?) and if it’s still invalid it should set a flag so that the MCU can read this and notify the user.
The MCU will also read the ID Register once it is done and updated and set the user interface accordingly.

STORE DATA:

Place into internal FIFO buffer of Channel N Controller
Notify the memory controller that there is data available from this channel
The memory controller scans through all channels and checks if data is available
The memory controller picks the highest prioritized channel and moves a chunk of data into the memory.
The memory controller does not care how the data is formatted, it only cares about moving X number of bytes from FIFOs to memory
The memory controller keeps track of the current write position for each channel and increments it when needed

Responsible for the communication between the MCU and FPGA
Data is transferred on request of the MCU
Saving data from the channels should have higher priority than reading it so if the MCU wants data it has to wait if one of the channels has to dump it’s data first
Use a FIFO to always get a chunk of data from the memory controller even though the MCU only wants a small piece of it???
Has a counter for sequential data access that auto-increments
For a transfer the MCU first sends information on what data to collect and then it can be read in sequence using DMA or something similar to get better performance