Relative logic signal evolution as displayed in the simulation datagraphs ?

[jongena]

In the evolution of various logic signals in the "usual type" (if I may call them like this) of datagraphs not all details are visible. Details on the exact relative behaviour between various signals can only be seen in the "single gate" datagraphs -- in as far as I understand. It this correct or am I missing still something else ? If correct, can more insight be given on how the various logic signals are displayed in the usual datagraph types and in the single gate displays ? And in essence... why not always show all exact relative timings ? Or am I missing an insight in the workings of the simulation ?