Getting parse errors when reading Verilog files using Lorina Verilog reader

[Maya7991]

I want to read a Verilog file using Lorina Verilog reader but I am getting parsing errors.

I am actually using Lorina as part of Mockturtle as I want to convert the input network read from Verilog file into a MIG network.

1. The following is my main.cpp

int main()
{
   std::string input_file, output_file, top;
   std::cout << "Enter the input verilog file name: "; // filename.v
   std::cin >> input_file;
   std::cout << "Enter the name of top module: ";
   std::cin >> top;

   diagnostics consumer;
   lorina::diagnostic_engine diag( &consumer );
   klut_network gate_network;

   if ( lorina::read_verilog( input_file, verilog_reader( gate_network, top ), &diag) != lorina::return_code::success )
   {
     fmt::print( "[e] Could not read input file `{}`\n", input_file );
     return -1;
   }
}

2. The input Verilog file for which the error occurs.

module full_adder(a, b, cin, S, Cout);
  input a, b, cin;
  output S,Cout;
  assign S = a ^ b ^ cin;
  assign Cout = (a & b) | (b & cin) | (a & cin); 
endmodule

3. Error messages or print-outs you see (if any) (preferably copy-pasted as-is).

[e] Diagnostic Message: `cannot parse expression on right-hand side of assign `Cout``
[e] Diagnostic Message: `cannot parse assign statement`
[e] Could not read input file `full_adder_1bit.v`

The statement assign Cout = (a & b) | (b & cin) | (a & cin); is not getting parsed and is throwing the above error as I understand.

Please help me understand the issue here. I tried raising an issue in Mockturtle(issue #624) but it was closed without the correct answer to this problem.

[aletempiac]

Answered in Mockturtle, issue #624.

For completeness, the solution is to write:
assign Cout = (a & b) | (a & cin) | (b & cin);
instead of
assign Cout = (a & b) | (b & cin) | (a & cin);

[hriener]

@Maya7991: We could support this in the parser. However, why don't you just dump it in the right order such that the parser would match it?