Merge pull request #16305 from unknownbrackets/ir-fpu

irjit: Fix unordered float compares
hrydgard · Oct 31, 2022 · 61ce0d0 · 61ce0d0
2 parents 3f33cf1 + 2da1bf7
commit 61ce0d0
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Showing 5 changed files with 16 additions and 8 deletions.
diff --git a/Core/MIPS/IR/IRCompALU.cpp b/Core/MIPS/IR/IRCompALU.cpp
@@ -118,7 +118,7 @@ void IRFrontend::Comp_RType3(MIPSOpcode op) {
 	MIPSGPReg rd = _RD;
 
 	// noop, won't write to ZERO.
-	if (rd == 0)
+	if (rd == MIPS_REG_ZERO)
 		return;
 
 	switch (op & 63) {
@@ -298,7 +298,7 @@ void IRFrontend::Comp_Allegrex2(MIPSOpcode op) {
 	MIPSGPReg rd = _RD;
 
 	// Don't change $zr.
-	if (rd == 0)
+	if (rd == MIPS_REG_ZERO)
 		return;
 
 	switch (op & 0x3ff) {

diff --git a/Core/MIPS/IR/IRCompFPU.cpp b/Core/MIPS/IR/IRCompFPU.cpp
@@ -118,7 +118,7 @@ void IRFrontend::Comp_FPUComp(MIPSOpcode op) {
 		break;
 	case 3:      // ueq, ngl (equal, unordered)
 		mode = IRFpCompareMode::EqualUnordered;
-		return;
+		break;
 	case 4:      // olt, lt (less than, ordered)
 		mode = IRFpCompareMode::LessOrdered;
 		break;

diff --git a/Core/MIPS/IR/IRCompVFPU.cpp b/Core/MIPS/IR/IRCompVFPU.cpp
@@ -464,6 +464,7 @@ namespace MIPSComp {
 				init = Vec4Init::AllONE;
 				break;
 			default:
+				INVALIDOP;
 				return;
 			}
 			ir.Write(IROp::Vec4Init, vec[0], (int)init);

diff --git a/Core/MIPS/IR/IRInterpreter.cpp b/Core/MIPS/IR/IRInterpreter.cpp
@@ -881,17 +881,23 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
 				break;
 			}
 			case IRFpCompareMode::EqualOrdered:
-			case IRFpCompareMode::EqualUnordered:
 				mips->fpcond = mips->f[inst->src1] == mips->f[inst->src2];
 				break;
+			case IRFpCompareMode::EqualUnordered:
+				mips->fpcond = mips->f[inst->src1] == mips->f[inst->src2] || my_isnan(mips->f[inst->src1]) || my_isnan(mips->f[inst->src2]);
+				break;
 			case IRFpCompareMode::LessEqualOrdered:
-			case IRFpCompareMode::LessEqualUnordered:
 				mips->fpcond = mips->f[inst->src1] <= mips->f[inst->src2];
 				break;
+			case IRFpCompareMode::LessEqualUnordered:
+				mips->fpcond = !(mips->f[inst->src1] > mips->f[inst->src2]);
+				break;
 			case IRFpCompareMode::LessOrdered:
-			case IRFpCompareMode::LessUnordered:
 				mips->fpcond = mips->f[inst->src1] < mips->f[inst->src2];
 				break;
+			case IRFpCompareMode::LessUnordered:
+				mips->fpcond = !(mips->f[inst->src1] >= mips->f[inst->src2]);
+				break;
 			}
 			break;
 

diff --git a/Core/MIPS/MIPSIntVFPU.cpp b/Core/MIPS/MIPSIntVFPU.cpp
@@ -1629,8 +1629,9 @@ namespace MIPSInt
 			d[cosineLane] = cosine;
 		}
 
-		// D prefix works, just not for x.
-		currentMIPS->vfpuCtrl[VFPU_CTRL_DPREFIX] &= 0xFFEFC;
+		// D prefix works, just not for the cosine lane.
+		uint32_t dprefixRemove = (3 << cosineLane) | (1 << (8 + cosineLane));
+		currentMIPS->vfpuCtrl[VFPU_CTRL_DPREFIX] &= 0xFFFFF ^ dprefixRemove;
 		ApplyPrefixD(d, sz);
 		WriteVector(d, sz, vd);
 		PC += 4;