GitHub - iamazizhaider/Single_Cycle_RiscV_Processor: This project was designed to run on Nexys A7 Artix-7 FPGA Trainer Board. This processor written in System Verilog can run I-Type, R-Type, B-Type, S-Type RISC-V commands. The current instruction set that has been uploaded here finds the greatest common divisor of two numbers.

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This project was designed to run on Nexys A7 Artix-7 FPGA Trainer Board. This processor written in System Verilog can run I-Type, R-Type, B-Type, S-Type RISC-V commands. The current instruction set that has been uploaded here finds the greatest common divisor of two numbers.

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU.sv		ALU.sv
ALUDecoder.sv		ALUDecoder.sv
AssemblyLanguageCode.txt		AssemblyLanguageCode.txt
BranchComparator.sv		BranchComparator.sv
Controller.sv		Controller.sv
DM_Data.mem		DM_Data.mem
DataMemory.sv		DataMemory.sv
DataPath.sv		DataPath.sv
FrequencyDivider.sv		FrequencyDivider.sv
IM_Data.mem		IM_Data.mem
ImmediateGen.sv		ImmediateGen.sv
InstructionMemory.sv		InstructionMemory.sv
MainDecoder.sv		MainDecoder.sv
RegisterFile.sv		RegisterFile.sv
RiscV_SS_Processor.sv		RiscV_SS_Processor.sv
TB.sv		TB.sv