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pcie.c
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pcie.c
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// SPDX-License-Identifier: ISC
/*
* Copyright (c) 2014 Broadcom Corporation
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/firmware.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/bcma/bcma.h>
#include <linux/sched.h>
#include <linux/sched/signal.h>
#include <linux/kthread.h>
#include <linux/io.h>
#include <asm/unaligned.h>
#include <soc.h>
#include <chipcommon.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <brcm_hw_ids.h>
/* Custom brcmf_err() that takes bus arg and passes it further */
#define brcmf_err(bus, fmt, ...) \
do { \
if (IS_ENABLED(CONFIG_BRCMDBG) || \
IS_ENABLED(CONFIG_BRCM_TRACING) || \
net_ratelimit()) \
__brcmf_err(bus, __func__, fmt, ##__VA_ARGS__); \
} while (0)
#include "debug.h"
#include "bus.h"
#include "commonring.h"
#include "msgbuf.h"
#include "pcie.h"
#include "firmware.h"
#include "chip.h"
#include "core.h"
#include "common.h"
enum brcmf_pcie_state {
BRCMFMAC_PCIE_STATE_DOWN,
BRCMFMAC_PCIE_STATE_UP
};
BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
BRCMF_FW_DEF(4364, "brcmfmac4364-pcie");
BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie");
BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie");
BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
BRCMF_FW_DEF(4355, "brcmfmac89459-pcie");
/* firmware config files */
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
/* per-board firmware binaries */
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin");
MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob");
static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFFFFF, 4355)
BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359),
BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFFF, 4364),
BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
};
static const struct brcmf_firmware_mapping brcmf_pcie_otp_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFFF, 4378B1), /* revision ID 3 */
};
#define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */
#define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
/* backplane addres space accessed by BAR0 */
#define BRCMF_PCIE_BAR0_WINDOW 0x80
#define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
#define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
#define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
#define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
#define BRCMF_PCIE_REG_INTSTATUS 0x90
#define BRCMF_PCIE_REG_INTMASK 0x94
#define BRCMF_PCIE_REG_SBMBX 0x98
#define BRCMF_PCIE_REG_LINK_STATUS_CTRL 0xBC
#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0 0x140
#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1 0x144
#define BRCMF_PCIE_64_PCIE2REG_INTMASK 0xC14
#define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT 0xC30
#define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK 0xC34
#define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0 0xA20
#define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1 0xA24
#define BRCMF_PCIE2_INTA 0x01
#define BRCMF_PCIE2_INTB 0x02
#define BRCMF_PCIE_INT_0 0x01
#define BRCMF_PCIE_INT_1 0x02
#define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
BRCMF_PCIE_INT_1)
#define BRCMF_PCIE_MB_INT_FN0_0 0x0100
#define BRCMF_PCIE_MB_INT_FN0_1 0x0200
#define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
#define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
#define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
#define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
#define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
#define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
#define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
#define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
#define BRCMF_PCIE_MB_INT_FN0 (BRCMF_PCIE_MB_INT_FN0_0 | \
BRCMF_PCIE_MB_INT_FN0_1)
#define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
BRCMF_PCIE_MB_INT_D2H0_DB1 | \
BRCMF_PCIE_MB_INT_D2H1_DB0 | \
BRCMF_PCIE_MB_INT_D2H1_DB1 | \
BRCMF_PCIE_MB_INT_D2H2_DB0 | \
BRCMF_PCIE_MB_INT_D2H2_DB1 | \
BRCMF_PCIE_MB_INT_D2H3_DB0 | \
BRCMF_PCIE_MB_INT_D2H3_DB1)
#define BRCMF_PCIE_64_MB_INT_D2H0_DB0 0x1
#define BRCMF_PCIE_64_MB_INT_D2H0_DB1 0x2
#define BRCMF_PCIE_64_MB_INT_D2H1_DB0 0x4
#define BRCMF_PCIE_64_MB_INT_D2H1_DB1 0x8
#define BRCMF_PCIE_64_MB_INT_D2H2_DB0 0x10
#define BRCMF_PCIE_64_MB_INT_D2H2_DB1 0x20
#define BRCMF_PCIE_64_MB_INT_D2H3_DB0 0x40
#define BRCMF_PCIE_64_MB_INT_D2H3_DB1 0x80
#define BRCMF_PCIE_64_MB_INT_D2H4_DB0 0x100
#define BRCMF_PCIE_64_MB_INT_D2H4_DB1 0x200
#define BRCMF_PCIE_64_MB_INT_D2H5_DB0 0x400
#define BRCMF_PCIE_64_MB_INT_D2H5_DB1 0x800
#define BRCMF_PCIE_64_MB_INT_D2H6_DB0 0x1000
#define BRCMF_PCIE_64_MB_INT_D2H6_DB1 0x2000
#define BRCMF_PCIE_64_MB_INT_D2H7_DB0 0x4000
#define BRCMF_PCIE_64_MB_INT_D2H7_DB1 0x8000
#define BRCMF_PCIE_64_MB_INT_D2H_DB (BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \
BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \
BRCMF_PCIE_64_MB_INT_D2H7_DB1)
#define BRCMF_PCIE_SHARED_VERSION_7 7
#define BRCMF_PCIE_MIN_SHARED_VERSION 5
#define BRCMF_PCIE_MAX_SHARED_VERSION BRCMF_PCIE_SHARED_VERSION_7
#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
#define BRCMF_PCIE_SHARED_HOSTRDY_DB1 0x10000000
#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
#define BRCMF_SHARED_RING_BASE_OFFSET 52
#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
#define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
#define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
#define BRCMF_RING_H2D_RING_MEM_OFFSET 4
#define BRCMF_RING_H2D_RING_STATE_OFFSET 8
#define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
#define BRCMF_RING_MAX_ITEM_OFFSET 4
#define BRCMF_RING_LEN_ITEMS_OFFSET 6
#define BRCMF_RING_MEM_SZ 16
#define BRCMF_RING_STATE_SZ 8
#define BRCMF_DEF_MAX_RXBUFPOST 255
#define BRCMF_CONSOLE_BUFADDR_OFFSET 8
#define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
#define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
#define BRCMF_D2H_DEV_D3_ACK 0x00000001
#define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
#define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
#define BRCMF_D2H_DEV_FWHALT 0x10000000
#define BRCMF_H2D_HOST_D3_INFORM 0x00000001
#define BRCMF_H2D_HOST_DS_ACK 0x00000002
#define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
#define BRCMF_H2D_HOST_D0_INFORM 0x00000010
#define BRCMF_PCIE_MBDATA_TIMEOUT msecs_to_jiffies(2000)
#define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
#define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
#define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
#define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
#define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
#define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
#define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
#define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
#define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
#define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
#define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
/* Magic number at a magic location to find RAM size */
#define BRCMF_RAMSIZE_MAGIC 0x534d4152 /* SMAR */
#define BRCMF_RAMSIZE_OFFSET 0x6c
struct brcmf_pcie_console {
u32 base_addr;
u32 buf_addr;
u32 bufsize;
u32 read_idx;
u8 log_str[256];
u8 log_idx;
};
struct brcmf_pcie_shared_info {
u32 tcm_base_address;
u32 flags;
struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
struct brcmf_pcie_ringbuf *flowrings;
u16 max_rxbufpost;
u16 max_flowrings;
u16 max_submissionrings;
u16 max_completionrings;
u32 rx_dataoffset;
u32 htod_mb_data_addr;
u32 dtoh_mb_data_addr;
u32 ring_info_addr;
struct brcmf_pcie_console console;
void *scratch;
dma_addr_t scratch_dmahandle;
void *ringupd;
dma_addr_t ringupd_dmahandle;
u8 version;
};
struct brcmf_pcie_core_info {
u32 base;
u32 wrapbase;
};
#define BRCMF_OTP_MAX_PARAM_LEN 16
struct brcmf_otp_params {
char module[BRCMF_OTP_MAX_PARAM_LEN];
char vendor[BRCMF_OTP_MAX_PARAM_LEN];
char version[BRCMF_OTP_MAX_PARAM_LEN];
bool valid;
};
struct brcmf_pciedev_info {
enum brcmf_pcie_state state;
bool in_irq;
struct pci_dev *pdev;
char fw_name[BRCMF_FW_NAME_LEN];
char nvram_name[BRCMF_FW_NAME_LEN];
char clm_name[BRCMF_FW_NAME_LEN];
const struct firmware *clm_fw;
const struct brcmf_pcie_reginfo *reginfo;
void __iomem *regs;
void __iomem *tcm;
u32 ram_base;
u32 ram_size;
struct brcmf_chip *ci;
u32 coreid;
struct brcmf_pcie_shared_info shared;
wait_queue_head_t mbdata_resp_wait;
bool mbdata_completed;
bool irq_allocated;
bool wowl_enabled;
u8 dma_idx_sz;
void *idxbuf;
u32 idxbuf_sz;
dma_addr_t idxbuf_dmahandle;
u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
u16 value);
struct brcmf_mp_device *settings;
struct brcmf_otp_params otp;
#ifdef DEBUG
u32 console_interval;
bool console_active;
struct timer_list timer;
#endif
};
struct brcmf_pcie_ringbuf {
struct brcmf_commonring commonring;
dma_addr_t dma_handle;
u32 w_idx_addr;
u32 r_idx_addr;
struct brcmf_pciedev_info *devinfo;
u8 id;
};
/**
* struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
*
* @ringmem: dongle memory pointer to ring memory location
* @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
* @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
* @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
* @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
* @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
* @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
* @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
* @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
* @max_flowrings: maximum number of tx flow rings supported.
* @max_submissionrings: maximum number of submission rings(h2d) supported.
* @max_completionrings: maximum number of completion rings(d2h) supported.
*/
struct brcmf_pcie_dhi_ringinfo {
__le32 ringmem;
__le32 h2d_w_idx_ptr;
__le32 h2d_r_idx_ptr;
__le32 d2h_w_idx_ptr;
__le32 d2h_r_idx_ptr;
struct msgbuf_buf_addr h2d_w_idx_hostaddr;
struct msgbuf_buf_addr h2d_r_idx_hostaddr;
struct msgbuf_buf_addr d2h_w_idx_hostaddr;
struct msgbuf_buf_addr d2h_r_idx_hostaddr;
__le16 max_flowrings;
__le16 max_submissionrings;
__le16 max_completionrings;
};
static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
};
static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
};
static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
};
struct brcmf_pcie_reginfo {
u32 intmask;
u32 mailboxint;
u32 mailboxmask;
u32 h2d_mailbox_0;
u32 h2d_mailbox_1;
u32 int_d2h_db;
u32 int_fn0;
};
static const struct brcmf_pcie_reginfo brcmf_reginfo_default = {
.intmask = BRCMF_PCIE_PCIE2REG_INTMASK,
.mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT,
.mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
.h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0,
.h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1,
.int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB,
.int_fn0 = BRCMF_PCIE_MB_INT_FN0,
};
static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = {
.intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK,
.mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT,
.mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK,
.h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0,
.h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1,
.int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB,
.int_fn0 = 0,
};
static void brcmf_pcie_setup(struct device *dev, int ret,
struct brcmf_fw_request *fwreq);
static struct brcmf_fw_request *
brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
static void
brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active);
static void brcmf_pcie_debugfs_create(struct device *dev);
static u16
brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
{
void __iomem *address = devinfo->regs + reg_offset;
return ioread16(address);
}
static u32
brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
{
void __iomem *address = devinfo->regs + reg_offset;
return (ioread32(address));
}
static void
brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
u32 value)
{
void __iomem *address = devinfo->regs + reg_offset;
iowrite32(value, address);
}
static u8
brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
{
void __iomem *address = devinfo->tcm + mem_offset;
return (ioread8(address));
}
static u16
brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
{
void __iomem *address = devinfo->tcm + mem_offset;
return (ioread16(address));
}
static void
brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
u16 value)
{
void __iomem *address = devinfo->tcm + mem_offset;
iowrite16(value, address);
}
static u16
brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
{
u16 *address = devinfo->idxbuf + mem_offset;
return (*(address));
}
static void
brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
u16 value)
{
u16 *address = devinfo->idxbuf + mem_offset;
*(address) = value;
}
static u32
brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
{
void __iomem *address = devinfo->tcm + mem_offset;
return (ioread32(address));
}
static void
brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
u32 value)
{
void __iomem *address = devinfo->tcm + mem_offset;
iowrite32(value, address);
}
static u32
brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
{
void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
return (ioread32(addr));
}
static void
brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
u32 value)
{
void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
iowrite32(value, addr);
}
static void
brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
void *dstaddr, u32 len)
{
void __iomem *address = devinfo->tcm + mem_offset;
__le32 *dst32;
__le16 *dst16;
u8 *dst8;
if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
dst8 = (u8 *)dstaddr;
while (len) {
*dst8 = ioread8(address);
address++;
dst8++;
len--;
}
} else {
len = len / 2;
dst16 = (__le16 *)dstaddr;
while (len) {
*dst16 = cpu_to_le16(ioread16(address));
address += 2;
dst16++;
len--;
}
}
} else {
len = len / 4;
dst32 = (__le32 *)dstaddr;
while (len) {
*dst32 = cpu_to_le32(ioread32(address));
address += 4;
dst32++;
len--;
}
}
}
#define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \
CHIPCREGOFFS(reg))
#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
CHIPCREGOFFS(reg), value)
static void
brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
{
const struct pci_dev *pdev = devinfo->pdev;
struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
struct brcmf_core *core;
u32 bar0_win;
core = brcmf_chip_get_core(devinfo->ci, coreid);
if (core) {
bar0_win = core->base;
pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
&bar0_win) == 0) {
if (bar0_win != core->base) {
bar0_win = core->base;
pci_write_config_dword(pdev,
BRCMF_PCIE_BAR0_WINDOW,
bar0_win);
}
}
} else {
brcmf_err(bus, "Unsupported core selected %x\n", coreid);
}
}
static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
{
struct brcmf_core *core;
u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
BRCMF_PCIE_CFGREG_PM_CSR,
BRCMF_PCIE_CFGREG_MSI_CAP,
BRCMF_PCIE_CFGREG_MSI_ADDR_L,
BRCMF_PCIE_CFGREG_MSI_ADDR_H,
BRCMF_PCIE_CFGREG_MSI_DATA,
BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
BRCMF_PCIE_CFGREG_RBAR_CTRL,
BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
u32 i;
u32 val;
u32 lsc;
if (!devinfo->ci)
return;
/* Disable ASPM */
brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
&lsc);
val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
val);
/* Watchdog reset */
brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
WRITECC32(devinfo, watchdog, 4);
msleep(100);
/* Restore ASPM */
brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
lsc);
core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
if (core->rev <= 13) {
for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
brcmf_pcie_write_reg32(devinfo,
BRCMF_PCIE_PCIE2REG_CONFIGADDR,
cfg_offset[i]);
val = brcmf_pcie_read_reg32(devinfo,
BRCMF_PCIE_PCIE2REG_CONFIGDATA);
brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
cfg_offset[i], val);
brcmf_pcie_write_reg32(devinfo,
BRCMF_PCIE_PCIE2REG_CONFIGDATA,
val);
}
}
}
static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
{
u32 config;
/* BAR1 window may not be sized properly */
brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
device_wakeup_enable(&devinfo->pdev->dev);
}
static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
{
if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
5);
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
0);
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
7);
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
0);
}
return 0;
}
static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
u32 resetintr)
{
struct brcmf_core *core;
if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
brcmf_chip_resetcore(core, 0, 0, 0);
}
if (!brcmf_chip_set_active(devinfo->ci, resetintr))
return -EIO;
return 0;
}
static int
brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
{
struct brcmf_pcie_shared_info *shared;
struct brcmf_core *core;
u32 addr;
u32 cur_htod_mb_data;
u32 i;
shared = &devinfo->shared;
addr = shared->htod_mb_data_addr;
cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
if (cur_htod_mb_data != 0)
brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
cur_htod_mb_data);
i = 0;
while (cur_htod_mb_data != 0) {
msleep(10);
i++;
if (i > 100)
return -EIO;
cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
}
brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
/* Send mailbox interrupt twice as a hardware workaround */
core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
if (core->rev <= 13)
pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
return 0;
}
static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
{
struct brcmf_pcie_shared_info *shared;
u32 addr;
u32 dtoh_mb_data;
shared = &devinfo->shared;
addr = shared->dtoh_mb_data_addr;
dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
if (!dtoh_mb_data)
return;
brcmf_pcie_write_tcm32(devinfo, addr, 0);
brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
}
if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
devinfo->mbdata_completed = true;
wake_up(&devinfo->mbdata_resp_wait);
}
if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
brcmf_fw_crashed(&devinfo->pdev->dev);
}
}
static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
{
struct brcmf_pcie_shared_info *shared;
struct brcmf_pcie_console *console;
u32 addr;
shared = &devinfo->shared;
console = &shared->console;
addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
console->base_addr, console->buf_addr, console->bufsize);
}
/**
* brcmf_pcie_bus_console_read - reads firmware messages
*
* @devinfo: pointer to the device data structure
* @error: specifies if error has occurred (prints messages unconditionally)
*/
static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
bool error)
{
struct pci_dev *pdev = devinfo->pdev;
struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
struct brcmf_pcie_console *console;
u32 addr;
u8 ch;
u32 newidx;
if (!error && !BRCMF_FWCON_ON())
return;
console = &devinfo->shared.console;
if (!console->base_addr)
return;
addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
newidx = brcmf_pcie_read_tcm32(devinfo, addr);
while (newidx != console->read_idx) {
addr = console->buf_addr + console->read_idx;
ch = brcmf_pcie_read_tcm8(devinfo, addr);
console->read_idx++;
if (console->read_idx == console->bufsize)
console->read_idx = 0;
if (ch == '\r')
continue;
console->log_str[console->log_idx] = ch;
console->log_idx++;
if ((ch != '\n') &&
(console->log_idx == (sizeof(console->log_str) - 2))) {
ch = '\n';
console->log_str[console->log_idx] = ch;
console->log_idx++;
}
if (ch == '\n') {
console->log_str[console->log_idx] = 0;
if (error)
__brcmf_err(bus, __func__, "CONSOLE: %s",
console->log_str);
else
pr_debug("CONSOLE: %s", console->log_str);
console->log_idx = 0;
}
}
}
static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
{
brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0);
}
static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
{
brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask,
devinfo->reginfo->int_d2h_db |
devinfo->reginfo->int_fn0);
}
static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
{
if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
brcmf_pcie_write_reg32(devinfo,
devinfo->reginfo->h2d_mailbox_1, 1);
}
static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
{
struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) {
brcmf_pcie_intr_disable(devinfo);
brcmf_dbg(PCIE, "Enter\n");
return IRQ_WAKE_THREAD;
}
return IRQ_NONE;
}
static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
{
struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
u32 status;
devinfo->in_irq = true;
status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
brcmf_dbg(PCIE, "Enter %x\n", status);
if (status) {
brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint,
status);
if (status & devinfo->reginfo->int_fn0)
brcmf_pcie_handle_mb_data(devinfo);
if (status & devinfo->reginfo->int_d2h_db) {
if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
brcmf_proto_msgbuf_rx_trigger(
&devinfo->pdev->dev);
}
}
brcmf_pcie_bus_console_read(devinfo, false);
if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
brcmf_pcie_intr_enable(devinfo);
devinfo->in_irq = false;
return IRQ_HANDLED;
}
static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
{
struct pci_dev *pdev = devinfo->pdev;
struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
brcmf_pcie_intr_disable(devinfo);
brcmf_dbg(PCIE, "Enter\n");
pci_enable_msi(pdev);
if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
brcmf_pcie_isr_thread, IRQF_SHARED,
"brcmf_pcie_intr", devinfo)) {
pci_disable_msi(pdev);
brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq);
return -EIO;
}
devinfo->irq_allocated = true;
return 0;
}
static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
{
struct pci_dev *pdev = devinfo->pdev;
struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
u32 status;
u32 count;
if (!devinfo->irq_allocated)
return;
brcmf_pcie_intr_disable(devinfo);
free_irq(pdev->irq, devinfo);
pci_disable_msi(pdev);
msleep(50);
count = 0;
while ((devinfo->in_irq) && (count < 20)) {
msleep(50);
count++;
}
if (devinfo->in_irq)
brcmf_err(bus, "Still in IRQ (processing) !!!\n");
status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status);