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It's possible to generate outputs using a Synthesizer and SynthBuilder rather than through Module.generateSynth. However, the SynthBuilder does not check that Module.build is called, only generateSynth does. This can produce unexpected outputs (e.g. SystemVerilog with no submodules) without any helpful error message indicating why.
To Reproduce
Use SynthBuilder to generate output verilog without calling build on the Module.
Expected behavior
ModuleNotBuiltException is thrown
Actual behavior
Silent incorrect results
Additional: Dart SDK info
No response
Additional: pubspec.yaml
No response
Additional: Context
No response
The text was updated successfully, but these errors were encountered:
Describe the bug
It's possible to generate outputs using a
Synthesizer
andSynthBuilder
rather than throughModule.generateSynth
. However, theSynthBuilder
does not check thatModule.build
is called, onlygenerateSynth
does. This can produce unexpected outputs (e.g. SystemVerilog with no submodules) without any helpful error message indicating why.To Reproduce
Use
SynthBuilder
to generate output verilog without callingbuild
on theModule
.Expected behavior
ModuleNotBuiltException
is thrownActual behavior
Silent incorrect results
Additional: Dart SDK info
No response
Additional: pubspec.yaml
No response
Additional: Context
No response
The text was updated successfully, but these errors were encountered: