Support multiple triggers on flops

[mkorbel1]

Is your feature request related to a problem? Please describe.
Support multiple triggers for flops, like in SystemVerilog:

always_ff @(posedge clk or posedge reset)

Describe the solution you'd like
The FF and FlipFlop should have a syntax that accepts a list of signals instead of a single clk signal.

Describe alternatives you've considered
Using something like clk | reset is insufficient because there could be a rising edge of reset during a clock high period.

[wswongat]

@mkorbel1 Is it possible to support negative edge trigger as well?
It seems like the rohd only support the positive edge single trigger with current version.

rohd/lib/src/modules/conditional.dart

Line 222 in eb4fd66

} else if (LogicValue.isPosedge(_preTickClkValue!, clk.bit)) {

[mkorbel1]

@wswongat it wouldn't be too hard to add that, but I figured it wasn't really needed as a separate feature since you could always just use the posedge of an inverted signal, for example:

FF(clk, [...]); //posedge of clk
FF(~clk, [...]); // negedge of clk

Do you think that meets your needs or can you elaborate why you think a separate negedge trigger would be beneficial beyond this?

[wswongat]

@mkorbel1 Your suggestion looks good. Looks like we need to find some way to support multiple triggers on flops

[mkorbel1]

@wswongat #65 should address this issue and provide support for multiple triggers on flops