Fix bugs related to module naming and instantiation

[mkorbel1]

Description & Motivation

• Fixed a bug where signal names and module instance names could conflict.
• Fixed a bug where in some cases modules might not be properly detected as sub-modules.

Related Issue(s)

Fix #205

Testing

• Added a new test to cover the sub-module bug
• Added a new suite of tests covering combinations of names for input ports, output ports, internal signals, internal module instance names, internal module definition names, containing module definition names, and containing module instance names

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

[chaparalas]

Does the dart static check flag an instance name = signal name ?

[mkorbel1]

Does the dart static check flag an instance name = signal name ?

Variable names in Dart are statically analyzed. Signal name and instance names are uniquified automatically, where allowed, when generating SystemVerilog. If names cannot be successfully uniquified (e.g. port names are guaranteed to be the maintained; it is possible to "reserve" an instance name of a module), then an error will be flagged during generation.